Multi-layer interconnect structure for stacked dies

• US 8,841,773 B2
• Filed: 09/10/2012
• Issued: 09/23/2014
• Est. Priority Date: 03/30/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Hung-Pin, Chiu, Chien-Ming, Wu, Tsang-Jiuh, Shue, Shau-Lin, Yu, Chen-Hua
• Primary Examiner(s): Parekh, Nitin
• Application Number:
  US13/608,456
• Publication Number:
  US 20130001799A1
• Time in Patent Office: 743 Days
• Field of Search: 257/758, 257/774, 257/E23.174
• US Class Current: 257/774
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13109 Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13116 Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/13139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13184 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/14181 On opposite sides of the body
• CPC Class Codes: H01L 23/525 with adaptable interconnections
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/14 of a plurality of bump connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01327 Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

A multi-layer interconnect structure for stacked die configurations is provided. Through-substrate vias are formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-substrate vias. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-substrate vias. A first conductive element is formed electrically coupled to respective ones of the through-substrate vias and extending over the isolation film. One or more additional layers of isolation films and conductive elements may be formed, with connection elements such as solder balls being electrically coupled to the uppermost conductive elements.

Claims

1. A semiconductor device comprising:

a first substrate;

a through-substrate via comprising a single continuous structure extending from a first side of the first substrate through the first substrate and protruding from a second side of the first substrate by a first distance, the through-substrate via electrically coupled to an electrical device disposed on the first side of the first substrate;

a first isolation film on the second side of the first substrate, the first isolation film having a thickness less than the first distance, wherein the through-substrate via is exposed above the first isolation film;

a first conductive element on the through-substrate via, the first conductive element extending over the first isolation film;

a second isolation film on the first isolation film and the first conductive element; and

a second conductive element electrically coupled to the first conductive element and extending over an upper surface of the second isolation film.

2. The semiconductor device of claim 1, wherein the first isolation film is a different material than the second isolation film.

3. The semiconductor device of claim 1, wherein at least one of the first isolation film and the second isolation film is a composite layer.

4. The semiconductor device of claim 1, further comprising a liner along sidewalls of the through-substrate via.

5. The semiconductor device of claim 1, further comprising a third isolation film over the second isolation film and the second conductive element.

6. The semiconductor device of claim 5, further comprising a connection element electrically coupled to the second conductive element.

7. A semiconductor device comprising:

through-substrate vias extending through a first substrate and in electrical contact with an electrical device on a frontside of the first substrate, the through-substrate vias protruding from a backside of the first substrate by a first distance;

a first isolation film on the backside of the first substrate between adjacent ones of the through-substrate vias, the first isolation film having a thickness less than the first distance;

liners disposed in the first substrate, each one of the liners in contact with respective ones of the through-substrate vias, the liners extending above a lower surface of the first isolation film;

first conductive elements being in electrical contact with respective ones of the through-substrate vias and extending over the first isolation film;

a second isolation film over the first conductive elements; and

second conductive elements being in electrical contact with respective ones of the first conductive elements and extending over the second isolation film.

8. The semiconductor device of claim 7, further comprising a third isolation film over the second redistribution layer and at least one of the second conductive elements.

9. The semiconductor device of claim 7, further comprising one or more connection elements, each of the one or more connection elements electrically coupled to at least one of the second conductive elements.

10. The semiconductor device of claim 7, wherein the through-substrate via is electrically coupled to the electrical device through one or more intermetal dielectric layers disposed on the frontside of the substrate.

11. The semiconductor device of claim 7, wherein a bottonmost surface of the first conductive elements extend below a topmost surface of the through vias.

12. A semiconductor device comprising:

a substrate having one or more through-substrate vias extending from a circuit-side to a backside of the substrate, wherein the backside of the substrate is recessed such that the through-substrate vias protrude from the backside of the substrate;

a first redistribution layer comprising;

a first isolation film over the backside of the substrate; and

first conductive elements electrically coupled to respective ones of the one or more through-substrate vias, respective ones of the one or more through-substrate vias extending above a lower surface of respective ones of the first conductive elements, the first conductive elements extending over an upper surface of the first isolation film; and

one or more additional redistribution layers, each additional redistribution layer comprising;

an additional isolation film over an uppermost isolation film; and

additional conductive elements electrically coupled to respective ones of the underlying conductive elements, the additional conductive elements extending over an upper surface of the respective additional isolation film.

13. The semiconductor device of claim 12 wherein the one or more through-substrate vias protrude from the backside the substrate by a first distance and wherein the first isolation film has a thickness less than the first distance.

14. The semiconductor device of claim 12 wherein the one or more through-substrate vias protrude through the first isolation film.

15. The semiconductor device of claim 12, wherein at least one of the one or more through-substrate vias is in electrical contact with a device disposed on the circuit-side of the substrate.

16. The semiconductor device of claim 12, further comprising a top isolation film over an uppermost redistribution layer.

17. The semiconductor device of claim 12, further comprising one or more connection elements, each of the one or more connection elements electrically coupled to at least one of the additional conductive elements of the uppermost redistribution layer.

18. The semiconductor device of claim 12, wherein the first isolation film is a different material than the additional isolation films of the one or more additional redistribution layers.

19. The semiconductor device of claim 12, wherein at least one of the first isolation film and additional isolation films are a composite layer.

20. The semiconductor device of claim 12, further comprising a liner along sidewalls of the through-substrate vias.