Dual-loop voltage regulator architecture with high DC accuracy and fast response time

• US 8,841,893 B2
• Filed: 08/19/2011
• Issued: 09/23/2014
• Est. Priority Date: 12/16/2010
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bulzacchelli, John F., Cox, Carrie E., Toprak-Deniz, Zeynep, Friedman, Daniel J., Iadanza, Joseph A., Rasmus, Todd M.
• Primary Examiner(s): Berhane, Adolf
• Assistant Examiner(s): Lee, Jye-June
• Application Number:
  US13/213,578
• Publication Number:
  US 20120153910A1
• Time in Patent Office: 1,131 Days
• Field of Search: 323/265, 323272-274, 323280-282, 323/284, 323/288, 363/73, 363/74, 363/123
• US Class Current: 323/280
• CPC Class Codes: G05F 1/575 characterised by the feedback circuit

Abstract

Dual-loop voltage regulator circuits and methods in which a dual-loop voltage regulation framework is implemented with a first inner loop having a bang-bang voltage regulator to achieve nearly instantaneous response time, and a second outer loop, which is slower in operating speed than the first inner loop, to controllably adjust a trip point of the bang-bang voltage regulator to achieve high DC accuracy.

Claims

1. A voltage regulator circuit, comprising:

an error amplifier to compare a first reference voltage and a regulated voltage at an output node of the voltage regulator circuit, and to generate a first control current and a second control current based on a result of comparing the first reference voltage and the regulated voltage;

a charge pump circuit, connected to an output of the error amplifier, to dynamically generate a second reference voltage in response to the first and second control currents generated by the error amplifier;

a comparator to compare the second reference voltage and the regulated voltage and generate a gate control signal based on a result of comparing the second reference voltage and the regulated voltage; and

a first passgate device connected to the output node, wherein the first passgate device is controlled by the gate control signal to be fully turned on/off in a bang-bang mode of operation to supply current to the output node.

2. The voltage regulator circuit of claim 1, wherein the charge pump circuit dynamically generates the second reference voltage by switchably applying the first and second control currents to a charge pump capacitor, connected at an output of the charge pump circuit, to charge and discharge the charge pump capacitor.

3. The voltage regulator circuit of claim 2, wherein the charge pump circuit comprises a switching circuit that is controlled by an inverted version of the gate control signal to switchably apply the first and second control currents to the charge pump capacitor.

4. The voltage regulator circuit of claim 2, wherein the charge pump circuit comprises a switching circuit that is controlled by a buffered version of the gate control signal to switchably apply the first and second control currents to the charge pump capacitor.

5. The voltage regulator circuit of claim 1, wherein the comparator comprises an input stage that is powered by the regulated voltage at the output node of the voltage regulator circuit.

6. The voltage regulator circuit of claim 1, wherein the charge pump circuit is powered by the regulated voltage at the output node of the voltage regulator circuit.

7. The voltage regulator circuit of claim 1, further comprising a first control circuit to generate a first control signal upon startup of the voltage regulator circuit to (i) turn on the first passgate device upon startup of the voltage regulator circuit to increase a voltage level of the regulated voltage at the output of the voltage regulator circuit to a predefined voltage level and to (ii) increase a voltage level of the second reference voltage.

8. The voltage regulator circuit of claim 1, further comprising:

a second passgate device, connected in parallel with the first passgate device; and

a second control system to calibrate a total passgate strength for supplying current to the output node, by selectively activating the second passgate device to operate in parallel with the first passgate device.

9. The voltage regulator circuit of claim 8, wherein the second control system generates a control signal that selectively activates a driver to drive the second passgate device, based on one of a plurality of supply voltage settings.

10. The voltage regulator of claim 8, wherein the second control system comprises:

a replica reference circuit to determine a maximum load current under real-time operating conditions; and

control logic to generate an activation control signal that selectively activates one of or both of the first and second passgate devices to provide minimum passgate strength sufficient to supply the determined maximum load current.

11. The voltage regulator of claim 10, wherein the first and second passgate devices are binary-weighted with respect to a common reference passgate device width, and wherein the activation control signal is an N-bit signal.

12. An integrated circuit chip comprising the voltage regulator of claim 1.

13. An integrated circuit, comprising:

a power grid;

a load circuit connected to the power grid; and

a distributed voltage regulator system comprising a voltage regulator control circuit and one or more micro-regulator control circuits, wherein each of the one or more micro-regulator control circuits has a respective output node connected to a different point on the power grid, and wherein each of the one or more micro-regulator control circuits are controlled by the voltage regulator control circuit to generate a respective regulated voltage at the respective output node of the micro-regulator control circuit to collectively supply a regulated voltage on the power grid to the load circuit,

wherein the voltage regulator control circuit comprises an error amplifier to compare a first reference voltage to a regulated voltage at a sense point of the power grid, and to generate a first control current and a second control current based on a result of comparing the first reference voltage and the regulated voltage at the sense point of the power grid; and

wherein each of the one or more micro-regulator control circuits comprises;

a charge pump circuit, connected to an output of the error amplifier, to dynamically generate a respective second reference voltage in response to the first and second control currents generated by the error amplifier;

a comparator to compare the respective second reference voltage and the respective regulated voltage at the respective output node of the micro-regulator control circuit, and generate a gate control signal based on a result of comparing the respective second reference voltage and the respective regulated voltage; and

a first passgate device connected to the respective output node, wherein the first passgate device is controlled in a bang-bang mode of operation by the gate control signal to supply current to the respective output node.

14. The integrated circuit of claim 13, wherein the charge pump circuit of each micro-regulator control circuit dynamically generates the respective second reference voltage by switchably applying the first and second control currents to a charge pump capacitor, connected at an output of the charge pump circuit, to charge and discharge the charge bump capacitor.

15. The integrated circuit of claim 14, wherein the charge pump circuit of each micro-regulator control circuit comprises a switching circuit that is controlled by an inverted version of the gate control signal to switchably apply the first and second control currents to the charge pump capacitor.

16. The integrated circuit of claim 14, wherein the charge pump circuit of each micro-regulator control circuit comprises a switching circuit that is controlled by a buffered version of the gate control signal to switchably apply the first and second control currents to the charge pump capacitor.

17. The integrated circuit of claim 13, wherein the comparator of each micro-regulator control circuit comprises an input stage that is powered by the respective regulated voltage at the respective output node of the micro-regulator control circuit.

18. The integrated circuit of claim 13, wherein the charge pump circuit of each micro-regulator control circuit is powered by the respective regulated voltage at the respective output node of the micro-regulator control circuit.

19. The integrated circuit of claim 13, further comprising a first control circuit to generate a first control signal upon startup of the distributed voltage regulator system to (i) turn on the first passgate device of each micro-regulator control circuit upon startup of the voltage regulator circuit to increase a voltage level of the respective regulated voltage at the respective output node of the micro-regulator control circuit to a predefined voltage level and to (ii) increase a voltage level of the respective second reference voltage.

20. The integrated circuit of claim 13, wherein each of the one or more micro-regulator control circuits further comprises a second passgate device, connected in parallel with the first passgate device;

and wherein the integrated circuit further comprises a second control system to calibrate a total passgate strength for each of the one or more micro-regulator control circuits to supply current to the respective output nodes, by selectively activating the second passgate device of the one or more micro-regulator control circuits to operate in parallel with the first passgate device.

21. The integrated circuit of claim 20, wherein the second control system generates a control signal that selectively activates a driver to drive the second passgate device, based on one of a plurality of supply voltage settings.

22. The integrated circuit of claim 20, wherein the second control system comprises:

a replica reference circuit to determine a maximum load current under current real-time operating conditions; and

control logic to generate an activation control signal that selectively activates one of or both of the first and second passgate devices to provide minimum passgate strength sufficient to supply the determined maximum load current.

23. The integrated circuit of claim 22, wherein the first and second passgate devices in each of the one or more micro-regulator control circuits are binary-weighted with respect to a common reference passgate device width.

24. A method for regulating voltage, comprising:

comparing a reference voltage with a regulated voltage;

generating a first control current and a second control current based on a result of comparing the reference voltage with the regulated voltage;

dynamically generating a second reference voltage based on the first and second control currents wherein dynamically generating a second reference voltage comprises outputting the first and second control currents to a charge pump circuit, and switchably applying the first and second control currents to a charge pump capacitor, connected at an output of the charge pump circuit, to charge and discharge the charge pump capacitor;

comparing the second reference voltage with the regulated voltage;

generating a gate control signal based on a result of comparing the second reference voltage with the regulated voltage; and

controlling a first passgate device in a bang-bang mode of operation using the gate control signal to supply current to a regulated voltage output node.

25. The method of claim 24, wherein switchably applying the first and second control currents to the charge pump capacitor comprises controlling a switching circuit of the charge pump circuit using an inverted version of the gate control signal to switchably apply the first and second control currents to the charge pump capacitor.