Probe card wiring structure

• US 8,841,931 B2
• Filed: 01/27/2011
• Issued: 09/23/2014
• Est. Priority Date: 01/27/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Kuo, Yung-Hsin, Hung, Wensen
• Primary Examiner(s): Hollington, Jermele M
• Assistant Examiner(s): MCANDREW, CHRISTOPHER P
• Application Number:
  US13/014,846
• Publication Number:
  US 20120194210A1
• Time in Patent Office: 1,335 Days
• Field of Search: 324/757.04
• US Class Current: 324/754.07
• CPC Class Codes: G01R 1/07378 using an intermediate adapter, e.g. space transformers G01R1/07371 takes precedence
• CPC Class Codes: Y10T 29/49144 by metal fusion

Abstract

The present disclosure provides a probe card for wafer level testing. The probe card includes a space transformer having first power/ground lines and first signal lines embedded therein, wherein the first power/ground and signal lines are configured to have a first wiring pitch on a first surface and a second wiring pitch on a second surface, the second wiring pitch being substantially less than the first wiring pitch; a printed circuit board bonded to the first surface of the space transformer, wherein the printed circuit board includes second power/ground lines and second signal lines embedded in the printed circuit board and coupled to the first power/ground and signal lines; and conductive lines configured to a surface of the printed circuit board remote to the first surface of the space transformer, wherein each of the conductive lines includes a first end coupled to one of the second signal lines and a second end coupled to a different location of the printed circuit board.

Claims

1. A method of preparing a wafer test system, comprising:

determining a probe card design to test a first wafer having a first type of device and a second wafer having a second type of device, wherein the second type of device having a different signal scheme, wherein the determining the design includes;

defining a space transformer having first power/ground lines and first signal lines embedded therein, wherein the first power/ground lines are disposed in an edge region of the space transformer and the first signal lines are disposed in a central region of the space transformer, the edge region surrounding the central region, and

defining a printed circuit board (PCB) bonded to the space transformer and embedded with second power/ground lines and second signal lines that are coupled to the first power/ground lines and signal lines, respectively, and wherein the second power/ground lines are disposed in an epoxy material edge region of the PCB and the second signal lines are disposed in an epoxy central region of the PCB, the edge region of the PCB surrounding the central region of the PCB;

fabricating a first and a second probe card according to the design;

adding a first set of conductive lines to the first probe card such that the first set of conductive lines are positioned above the PCB and each conductive line having two ends attached to a surface of the PCB remote to the space transformer, wherein the adding the conductive lines is based on the signal scheme of the first device;

adding a second set of conductive lines to the second probe card such that the second conductive lines are positioned above the PCB and each conductive line having two ends attached to a surface of the PCB remote to the space transformer, wherein the adding the conductive lines is based on the signal scheme of the second device.

2. The method of preparing a wafer test system of claim 1, wherein for the first and second sets of conductive lines, each of the conductive lines includes a first end coupled to one of the second signal lines and a second end attached to the printed circuit board at a location a distance away from the first end.

3. The method of preparing a wafer test system of claim 2, wherein the second end is connected to the connection cable.

4. The method of preparing a wafer test system of claim 1, wherein the first power/ground and signal lines are configured to have a first wiring pitch on a first surface and a second wiring pitch on a second surface, the second wiring pitch being substantially less than the first wiring pitch.

5. The method of preparing a wafer test system of claim 4, wherein fabricating the probe card includes providing the second power/ground lines and second signal lines are coupled to the first power/ground and signal lines, respectively.

6. The method of preparing a wafer test system of claim 1, wherein the first and second sets of conductive lines include one of metal and metal alloy and are attached to the printed circuit board by manual soldering.

7. The method of preparing a wafer test system of claim 1, wherein the first and second sets of conductive lines are the conductive lines that include a coaxial cable for signal and corresponding ground return wiring.

8. The method of preparing a wafer test system of claim 1, wherein the conductive lines include flex ribbon cables.

9. A method of making a probe card, comprising:

providing a first and second space transformer and a first and second printed circuit board having signal lines embedded therein wherein the signal lines are configured in a standard design for multiple wafers, each of a first type of wafer and a second type of wafer, wherein the first and second types have a different signal line scheme;

bonding the first space transformer to a first surface of the first printed circuit board having signal lines embedded therein;

determining a first configuration of conductive lines to test the first type of wafer; and

forming conductive lines over a second surface of the first printed circuit board according to the first configuration, wherein the second surface opposes the first surface, and wherein each of the conductive lines has a first end bonded to one of the signal lines on the second surface of the first printed circuit board and a second end bonded to a different region of the second surface of the first printed circuit board and wherein each of the conductive lines includes a length between the first end and the second end that is disposes a distance above the second surface of the first printed circuit board;

determining a second configuration of conductive lines to test the second type of wafer; and

forming conductive lines over a second surface of the second printed circuit board according to the first configuration, wherein the second surface opposes the first surface, and wherein each of the conductive lines has a first end bonded to one of the signal lines on the second surface of the second printed circuit board and a second end bonded to a different region of the second surface of the second printed circuit board.

10. The method of claim 9, wherein the forming conductive lines on the first and second printed circuit board includes bonding the conductive lines to the printed circuit board by manual soldering.

11. The method of claim 9, wherein the forming conductive lines on the first and second printed circuit board includes forming the conductive lines selected from the group consisting of coaxial cables and flex ribbon cables.