Partial block erase architecture for flash memory

• US 8,842,472 B2
• Filed: 05/21/2010
• Issued: 09/23/2014
• Est. Priority Date: 03/07/2007
• Status: Active Grant

• Current Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Inventors: Kim, Jin-Ki
• Primary Examiner(s): NGUYEN, VAN THU T
• Application Number:
  US12/785,099
• Publication Number:
  US 20100226183A1
• Time in Patent Office: 1,586 Days
• Field of Search: 365/185.09 O, 365/185.29 X, 365/185.33 X, 711/203, 711/206.X
• US Class Current: 365/185.09
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/344 Arrangements for verifying correct erasure or for detecting overerased cells
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles

Abstract

A method and system for increasing the lifespan of a flash memory device by selectively erasing sub-blocks of a memory block. Each physical memory block of the flash memory device is dividable into at least two logical sub-blocks, where each of the at least two logical sub-blocks is erasable. Therefore, only the data of the logical sub-block is erased and reprogrammed while unmodified data in the other logical sub-block avoids unnecessary program/erase cycles. The logical sub-blocks to be erased are dynamically configurable in size and location within the block. A wear leveling algorithm is used for distributing data throughout the physical and logical sub-blocks of the memory array to maximize the lifespan of the physical blocks during programming and data modification operations.

Claims

1. A method for wear leveling control in a memory device having a memory bank, the memory bank including memory blocks and each of the memory blocks including at least two sub-blocks, wherein a memory block is defined by a NAND memory cell string and sequentially programmable from a first wordline to a last wordline, and a lowest ranking sub-block includes a set of wordlines including the first wordline, the method comprising:

programming modified data to an empty sub-block of a new memory block; and

erasing a sub-block of the memory block containing an unmodified version of the modified data.

2. The method of claim 1, wherein the empty sub-block is the lowest ranking available sub-block of the new memory block.

3. The method of claim 1, wherein the empty sub-block has a ranking equal to the sub-block, where the empty sub-block of the new memory block and the sub-block of the memory block have wordlines addressed by logically common wordline addresses.

4. The method of claim 2, wherein the new memory block is empty.

5. The method of claim 3, wherein the new memory block includes other data stored in another sub-block having a lower ranking than the empty sub-block, the another sub-block being addressed by a set of wordline addresses different from the logically common wordline addresses.

6. The method of claim 1, wherein the empty sub-block has a ranking higher than the sub-block, the empty sub-block being addressed by a first set of wordline addresses and the sub-block being addressed by a second set of wordline addresses different from the first set of wordline addresses.

7. The method of claim 1, further including swapping data in the sub-block with other data in one other sub-block of the memory block when a difference between program/erase cycles of the sub-block and the one other sub-block reaches a predetermined value.

8. The method of claim 1, including receiving a command, and determining if the command is to program new data or for modifying data.

9. The method of claim 8, further including programming the new data to a lowest ranking available sub-block between the memory block and the new memory block when the command is to program new data.

10. The method of claim 1, further including updating an address mapping table to map a logical address of the modified data to a physical address corresponding to the empty sub-block of the new memory block.

11. The method of claim 8, further including sorting the memory blocks in a predetermined order, when the command is for modifying data.

12. The method of claim 11, wherein sorting the memory blocks includes ordering the memory blocks by an assigned physical position of the memory blocks.

13. The method of claim 11, wherein sorting the memory blocks includes ordering the memory blocks by an assigned logical position of the memory blocks.

14. The method of claim 11, wherein sorting the memory blocks includes ordering the memory blocks based on an occupancy rate of the memory blocks.

15. The method of claim 14, wherein sorting the memory blocks further includes scanning an address mapping table of the memory blocks for determining which sub-blocks are empty.

16. The method of claim 11, wherein sorting the memory blocks includes ordering the memory blocks based on a number of program/erase cycles.

17. The method of claim 16, wherein sorting the memory blocks further includes scanning an address mapping table of the memory blocks for determining the number of program/erase cycles for each memory block.

18. The method of claim 1, including selecting the empty sub-block of the new memory block for programming of the modified data, with a ranking equal to, less than or greater than the sub-block.

19. The method of claim 18, wherein an empty sub-block having a ranking greater than the sub-block is selected when a sub-block of the new memory block having a ranking equal to the sub-block is not empty.

20. The method of claim 19, wherein selecting includes selecting another new memory block for selecting the empty sub-block, when a sub-block of the new memory block having a ranking equal to the sub-block is empty, and the new memory block includes a programmed sub-block having a ranking greater than the sub-block.

21. The method of claim 20, wherein a lowest ranking empty sub-block of the new memory block is selected when the new memory block is empty.

22. The method of claim 21, wherein the empty sub-block having a ranking equal to the sub-block is selected when the new memory block includes a programmed sub-block having a ranking less than the sub-block.

23. A flash memory device, comprising:

a memory bank having rows of memory cells connected to wordlines and arranged as memory blocks, each of the memory blocks being defined by a respective NAND memory cell string;

a first memory block within the memory bank including at least two sub-blocks;

a second memory block within the memory bank including at least two sub-blocks, the second memory block configured to be sequentially programmed from a first wordline to a last wordline;

a lowest ranking sub-block of the second memory block including a set of wordlines that includes the first wordline;

an empty sub-block of the second memory block configured to be programmed to include modified data; and

,

a sub-block of the first memory block configured to contain an unmodified version of the modified data, and being further configured to be erased after the modified data is programmed to the empty sub-block.

24. The flash memory device of claim 23, wherein the empty sub-block is the lowest ranking available sub-block of the second memory block.

25. The flash memory device of claim 24, wherein the second memory block is empty.

26. The flash memory device of claim 23, wherein the empty sub-block has a ranking equal to the sub-block, where the empty sub-block of the second memory block and the sub-block of the first memory block have wordlines addressed by logically common wordline addresses.

27. The flash memory device of claim 26, wherein the second memory block includes other data stored in another sub-block having a lower ranking than the empty sub-block, the another sub-block being addressed by a set of wordline addresses different from the logically common wordline addresses.

28. The flash memory device of claim 23, wherein the empty sub-block has a ranking higher than the sub-block, the empty sub-block being addressed by a first set of wordline addresses and the sub-block being addressed by a second set of wordline addresses different from the first set of wordline addresses.