Partitioned radio-frequency apparatus and associated methods

• US 8,843,080 B2
• Filed: 12/31/2012
• Issued: 09/23/2014
• Est. Priority Date: 01/12/2001
• Status: Expired due to Fees

• Current Assignee: Silicon Laboratories Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Kerth, Donald, Behrens, Richard, Scott, Jeffrey, Vishakhadatta, G. Diwakar, Tuttle, G. Tyson, Srinivasan, Vishnu
• Primary Examiner(s): Lee, John J
• Application Number:
  US13/731,110
• Publication Number:
  US 20130208832A1
• Time in Patent Office: 631 Days
• Field of Search: 455/75, 455/74, 455/88, 455/313, 455/191.1, 455/552.1, 455/86, 455/77, 455/78, 455/83, 455/232.1, 455/255, 455/234.1, 455/189.1, 455/553.1, 455/333, 455/190.1
• US Class Current: 455/73
• CPC Class Codes: H04B 1/0003 Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain digital baseband systems H04L25/00; digital modulation/demodulation H04L27/00; CDMA H04B1/707; TDMA H04B7/2643; image transmission H04N5/00
• CPC Class Codes: H04B 1/109 by improving strong signal performance of the receiver when strong unwanted signals are present at the receiver input
• CPC Class Codes: H04B 1/28 the receiver comprising at least one semiconductor device having three or more electrodes
• CPC Class Codes: H04B 1/406 with more than one transmission mode, e.g. analog and digital modes
• CPC Class Codes: H04B 15/02 Reducing interference from electric apparatus by means located at or near the interfering apparatus
• CPC Class Codes: H04B 15/04 the interference being caused by substantially sinusoidal oscillations, e.g. in a receiver or in a tape-recorder
• CPC Class Codes: H04B 2215/064 Reduction of clock or synthesizer reference frequency harmonics

Abstract

Radio-frequency (RF) apparatus includes receiver analog circuitry that receives an RF signal and provides at least one digital signal to receiver digital circuitry that functions in cooperation with the receiver analog circuitry. The receiver analog circuitry and the receiver digital circuitry are partitioned so that interference effects between the receiver analog circuitry and the receiver digital circuitry tend to be reduced.

Claims

1. An electronic device for processing radio-frequency (RF) signals, the electronic device comprising:

a first circuit partition fabricated on a substrate of the electronic device, the first circuit partition comprising a down-converter to receive an RF signal and to generate an in-phase (I) signal and a quadrature (Q) signal, and an analog-to-digital converter (ADC) coupled to convert the in-phase signal and the quadrature signal to a first digital in-phase signal and a first digital quadrature signal; and

a second circuit partition fabricated on the substrate of the electronic device, the second circuit partition comprising a digital down-converter coupled to receive the first digital in-phase signal and the first digital quadrature signal and to generate a second digital in-phase signal and a second digital quadrature signal, and a digital filter coupled to filter the second digital in-phase signal and the second digital quadrature signal to generate a third digital in-phase signal and a third digital quadrature signal.

2. The electronic device according to claim 1, wherein the first circuit partition further comprises a low-noise amplifier (LNA), coupled to amplify an input signal of the electronic device, and to provide the RF signal to the down-converter.

3. The electronic device according to claim 1, wherein the first circuit partition further comprises a first programmable-gain amplifier (PGA), coupled to receive the in-phase signal from the down-converter, and to provide an amplified in-phase signal to the ADC;

and a second PGA, coupled to receive the quadrature signal from the down-converter, and to provide an amplified quadrature signal to the ADC.

4. The electronic device according to claim 1, wherein the second circuit partition further includes a first digital PGA coupled to receive the third digital in-phase signal, and to generate an amplified digital in-phase signal;

and a second digital PGA coupled to receive the third digital quadrature signal, and to generate an amplified digital quadrature signal.

5. The electronic device according to claim 1, further comprising a third circuit partition fabricated on the substrate of the electronic device, the third circuit partition comprising a local oscillator (LO) coupled to provide a RF LO signal to the down-converter.

6. The electronic device according to claim 1, wherein the second circuit partition further comprises digital-signal processing (DSP) circuitry coupled to receive the third digital in-phase signal and the third digital quadrature signal.

7. The electronic device according to claim 1, wherein the second circuit partition further comprises baseband processor circuitry coupled to receive the third digital in-phase signal and the third digital quadrature signal.

8. The electronic device according to claim 1, wherein the first and second circuit partitions are configured to operate as an intermediate-frequency (IF) receiver.

9. The electronic device according to claim 8, wherein the first and second circuit partitions are configured to operate as a low IF receiver.

10. The electronic device according to claim 1, wherein the first digital in-phase signal and the first digital quadrature signal are provided as one-bit signals.

11. An electronic device for processing radio-frequency (RF) signals, the electronic device comprising:

a first circuit partition fabricated on a substrate of the electronic device, the first circuit partition comprising a down-converter to receive an RF signal and to generate an in-phase (I) signal and a quadrature (Q) signal; and

a second circuit partition fabricated on the substrate of the electronic device, the second circuit partition comprising an analog-to-digital converter (ADC) coupled to convert the in-phase signal and the quadrature signal to a first digital in-phase signal and a first digital quadrature signal, a digital down-converter coupled to receive the first digital in-phase signal and the first digital quadrature signal and to generate a second digital in-phase signal and a second digital quadrature signal, and a digital filter coupled to filter the second digital in-phase signal and the second digital quadrature signal to generate a third digital in-phase signal and a third digital quadrature signal.

12. The electronic device according to claim 11, wherein the first circuit partition further comprises a low-noise amplifier (LNA), coupled to amplify an input signal of the electronic device, and to provide the RF signal to the down-converter.

13. The electronic device according to claim 11, further comprising a third circuit partition fabricated on the substrate of the electronic device, the third circuit partition comprising a local oscillator (LO) coupled to provide a RF LO signal to the down-converter.

14. The electronic device according to claim 11, wherein the second circuit partition further comprises baseband processor circuitry coupled to receive the third digital in-phase signal and the third digital quadrature signal.

15. The electronic device according to claim 11, wherein the first and second circuit partitions are configured to operate as a low intermediate-frequency (IF) receiver.

16. A method of processing radio-frequency (RF) signals, the method comprising:

receiving an RF signal in a first circuit partition fabricated on a substrate of an electronic device;

down-converting the RF signal in the first circuit partition to generate an in-phase (I) signal and a quadrature (Q) signal;

converting, using an analog-to-digital converter (ADC) in the first circuit partition, the in-phase signal and the quadrature signal to a first digital in-phase signal and a first digital quadrature signal;

digitally down-converting the first digital in-phase signal and the first digital quadrature signal in a second circuit partition fabricated on the substrate of an electronic device to generate a second digital in-phase signal and a second digital quadrature signal; and

digitally filtering the second digital in-phase signal and the second digital quadrature signal in the second circuit partition to generate a third digital in-phase signal and a third digital quadrature signal.

17. The method according to claim 16, further comprising amplifying, with a low-noise amplifier (LNA) in the first circuit partition, an input signal of the electronic device to provide the RF signal to the down-converter.

18. The method according to claim 16, further comprising generating, using a local oscillator (LO) in a third circuit partition fabricated on the substrate of the electronic device, to provide an RF LO signal to the down-converter.

19. The method according to claim 16, receiving the third digital in-phase signal and the third digital quadrature signal in baseband processor circuitry in the second circuit partition.

20. The method according to claim 16, further comprising operating the first and second circuit partitions as a low intermediate-frequency (IF) receiver.