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Hybrid address mutex mechanism for memory accesses in a network processor

  • US 8,843,682 B2
  • Filed: 09/30/2011
  • Issued: 09/23/2014
  • Est. Priority Date: 05/18/2010
  • Status: Expired due to Fees
First Claim
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1. A method of arbitrating access to a level one (L1) cache of a network processor implemented as an integrated circuit, the network processor having a plurality of processing modules and at least one shared memory, the processing modules coupled to at least one unidirectional ring bus, the method comprising:

  • defining, by the network processor, one or more virtual pipelines of the plurality of processing modules through the at least one unidirectional ring bus, each virtual pipeline defining a processing order of packet data received by the network processor through two or more of the plurality of processing modules, each virtual pipeline identified by a virtual pipeline identifier, wherein the defining accounts for non-sequential processing of the packet data;

    sending, by a source one of the plurality of processing modules, a task over the at least one unidirectional ring bus to an adjacent processing module coupled to the ring bus, the task corresponding to the received data packet and having a corresponding virtual pipeline identifier, the task including shared parameters that point to a shared parameter table stored in a system memory, wherein the sending the task includes task enqueue, scheduling and dequeue operations based on the shared parameters;

    iteratively;

    determining, by the adjacent processing module, based on the virtual pipeline identifier, whether the processing module is a destination processing module of the virtual pipeline associated with the task and, if not, passing the task unchanged to a next adjacent processing module coupled to the ring bus, thereby passing the task from the source processing module to each corresponding destination processing module on the ring bus;

    generating, by each destination processing module, one or more memory access requests, each memory access request comprising a requested address and an ID value corresponding to the requesting processing module, wherein each memory access request comprises one of a locked access request and one or more simple access requests;

    determining, by an address mutually exclusive (mutex) arbiter of the network processor, whether one or more received memory access requests are simple access requests or locked access requests, wherein, for each locked access request, the address mutex arbiter performs the steps of;

    determining, by the address mutex arbiter, whether two or more of the memory access requests are either conflicted or non-conflicted based on the requested address of each of the one or more memory access requests;

    if one or more of the memory access requests are non-conflicted, determining, by the address mutex arbiter, for each non-conflicted memory access request, whether the requested address of each non-conflicted memory access request is locked out by one or more prior memory access requests based on a lock table of the address mutex arbiter;

    if one or more of the non-conflicted memory access requests are locked-out by one or more prior memory access requests;

    queuing, by the address mutex arbiter, one or more locked-out memory requests;

    granting one or more non-conflicted memory access requests that are not locked-out;

    updating the lock table corresponding to the requested addresses associated with the one or more granted memory access requests.

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