System and method of page buffer operation for memory devices

• US 8,843,694 B2
• Filed: 11/22/2011
• Issued: 09/23/2014
• Est. Priority Date: 02/22/2007
• Status: Active Grant

• Current Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Inventors: Pyeon, Hong Beom, Kim, Jin-Ki, Oh, HakJune
• Primary Examiner(s): DUDEK JR, EDWARD J
• Application Number:
  US13/302,413
• Publication Number:
  US 20120066442A1
• Time in Patent Office: 1,036 Days
• Field of Search: 711/103, 711/118, 711/154, 710/52
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure
• CPC Class Codes: G06F 2212/1044 Space efficiency improvement
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/3042 being part of a memory device, e.g. cache DRAM
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G11C 2207/2245 Memory devices with an internal cache buffer
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/106 Data output latches
• CPC Class Codes: G11C 7/1087 Data input latches

Abstract

Systems and methods are provided for using page buffers of memory devices connected to a memory controller through a common bus. A page buffer of a memory device is used as a temporary cache for data which is written to the memory cells of the memory device. This can allow the memory controller to use memory devices as temporary caches so that the memory controller can free up space in its own memory.

Claims

1. A method for use in a memory system comprising a flash memory controller for communicating with a plurality of memory devices in a multi-drop architecture, the flash memory controller comprising a data storage, each of the plurality of memory devices comprising a page buffer and flash memory cells, the method comprising:

a) the flash memory controller outputting a command, an enable signal for designating one of the plurality of memory devices, and data from the data storage of the flash memory controller, the command instructing the designated memory device to temporarily store the outputted data in the page buffer of the selected device;

b) in response to the command and the enable signal, the designated memory device temporarily storing the outputted data in the page buffer of the designated device; and

repeating a) and b) to store further data from the data storage until no more temporary storage for data is needed,

wherein repeating a) and b) comprises repeating a) and b) to store data from the data storage to the page buffer of at least one further designated memory device until no more temporary storage for data is needed such that the page buffers of the designated memory devices collectively function as a cache.

2. The method of claim 1 further comprising:

when no more temporary storage for data is needed, freeing up space in the data storage containing the data that is now also stored in the page buffers of the designated devices.

3. The method of claim 1 further comprising:

to access the data temporarily stored in the page buffers of the designated memory devices, for each of the designated memory devices in sequence, the flash memory controller outputting a respective command and a respective enable signal that designates the designated memory device, the command instructing the designated memory device to read data from the page buffer of the designated memory device and pass this to the memory controller.

4. The method of claim 3 further comprising:

the flash memory controller storing the accessed data to the data storage of the flash memory controller.

5. The method of claim 1 wherein:

the flash memory controller outputting the command and the enable signal comprises sending the enable signal on a dedicated connection to the designated memory device.

6. A method for use in a memory system comprising a flash memory controller for communicating with a plurality of memory devices in a multi-drop architecture, the flash memory controller comprising a data storage, each of the plurality of memory devices comprising a page buffer and flash memory cells, the method comprising:

a) the flash memory controller outputting a command, an enable signal for designating one of the plurality of memory devices, and data from the data storage of the flash memory controller, the command instructing the designated memory device to temporarily store the outputted data in the page buffer of the selected device;

b) in response to the command and the enable signal, the designated memory device temporarily storing the outputted data in the page buffer of the designated device; and

repeating a) and b) to store further data from the data storage until no more temporary storage for data is needed,

the method further comprising;

to access the data temporarily stored in the page buffer of the designated memory device, the flash memory controller outputting a command and an enable signal that designates the designated memory device, the command instructing the designated memory device to read data from the page buffer of the designated memory device and pass this to the memory controller.

7. The method of claim 6 wherein each command that instructs one of the designated memory devices to read data from the page buffer of the designated memory device and pass this to the memory controller contains an operation code that is distinct from an operation code used to read data from the flash memory cells of a designated memory device.

8. The method of claim 7 wherein the operation code is for a burst data read.

9. The method of claim 6 further comprising:

the flash memory controller storing the accessed data to the data storage of the flash memory controller.

10. The method of claim 6 wherein:

the flash memory controller outputting the command and the enable signal comprises sending the enable signal on a dedicated connection to the designated memory device.

11. A method for use in a memory system comprising a flash memory controller for communicating with a plurality of memory devices in a multi-drop architecture, the flash memory controller comprising a data storage, each of the plurality of memory devices comprising a page buffer and flash memory cells, the method comprising:

a) the flash memory controller outputting a command, an enable signal for designating one of the plurality of memory devices, and data from the data storage of the flash memory controller, the command instructing the designated memory device to temporarily store the outputted data in the page buffer of the selected device;

b) in response to the command and the enable signal, the designated memory device temporarily storing the outputted data in the page buffer of the designated device; and

repeating a) and b) to store further data from the data storage until no more temporary storage for data is needed,

wherein the command that instructs the designated memory device to temporarily store the outputted data contained in the page buffer of the designated device contains an operation code that is distinct from an operation code of a command used to store data in the flash memory cells of a designated memory device.

12. The method of claim 11 wherein the operation code is for a burst data load.

13. The method of claim 11 wherein:

the flash memory controller outputting the command and the enable signal comprises sending the enable signal on a dedicated connection to the designated memory device.

14. A memory system comprising:

a plurality of memory devices each comprising a page buffer and flash memory cells;

a flash memory controller connected to the plurality of memory devices in a multi-drop architecture, the flash memory controller comprising a data storage;

the memory system configured to use at least one page buffer as a cache by;

a) the flash memory controller outputting a command and an enable signal for designating one of the plurality of designated memory devices, and data from the data storage of the memory controller, the command instructing the designated memory device to temporarily store the outputted data in the page buffer of the designated device;

b) in response to the command and the enable signal, the designated memory device temporarily storing the outputted data in the page buffer of the designated device; and

repeating a) and b) to store further data from the data storage until no more temporary storage for data is needed,

wherein repeating a) and b) comprises repeating a) and b) to store data from the data storage to the page buffer of at least one further designated memory device until no more temporary storage for data is needed such that the page buffers of the designated memory devices collectively function as a cache.

15. The memory system of claim 14 further configured to:

when no more temporary storage for data is needed, free up space in the data storage containing the data that is now also stored in the page buffers of the designated devices.

16. The memory system of claim 14 further configured:

to access the data temporarily stored in the page buffers of the designated memory devices, for each of the designated memory devices in sequence, the flash memory controller outputting a respective command and a respective enable signal that enables the designated memory device, the command instructing the designated memory device to read data from the page buffer of the designated memory device and pass this to the memory controller.

17. The memory system of claim 16 wherein the flash memory controller is further configured to store the accessed data to the data storage of the flash memory controller.

18. The memory system of claim 16 wherein the flash memory controller is further configured to store the accessed data to the data storage of the flash memory controller.

19. The memory system of claim 14 wherein:

the flash memory controller outputting the command and the enable signal comprises sending the enable signal on a dedicated connection to the designated memory device.

20. The memory system of claim 14 further comprising:

for each memory device, a dedicated connection from the memory controller to the memory device for sending a signal to enable the memory device.

21. A memory system comprising:

a plurality of memory devices each comprising a page buffer and flash memory cells;

a flash memory controller connected to the plurality of memory devices in a multi-drop architecture, the flash memory controller comprising a data storage;

the memory system configured to use at least one page buffer as a cache by;

a) the flash memory controller outputting a command and an enable signal for designating one of the plurality of designated memory devices, and data from the data storage of the memory controller, the command instructing the designated memory device to temporarily store the outputted data in the page buffer of the designated device;

b) in response to the command and the enable signal, the designated memory device temporarily storing the outputted data in the page buffer of the designated device; and

repeating a) and b) to store further data from the data storage until no more temporary storage for data is needed,

the memory system further configured;

to access the data temporarily stored in the page buffer of the designated memory device, the flash memory controller outputting a command and an enable signal that enables the designated memory device, the command instructing the designated memory device to read data from the page buffer of the designated memory device and pass this to the memory controller.

22. The memory system of claim 21 each command that instructs one of the designated memory devices to read data from the page buffer of the designated memory device and pass this to the memory controller contains an operation code that is distinct from an operation code used to read data from the flash memory cells of a designated memory device.

23. The memory system of claim 22 wherein the operation code is for a burst data read.

24. The memory system of claim 21 wherein the flash memory controller is further configured to store the accessed data to the data storage of the flash memory controller.

25. The memory system of claim 21 wherein the flash memory controller is further configured to store the accessed data to the data storage of the flash memory controller.

26. The memory system of claim 21 wherein:

the flash memory controller outputting the command and the enable signal comprises sending the enable signal on a dedicated connection to the designated memory device.

27. A memory system comprising:

a plurality of memory devices each comprising a page buffer and flash memory cells;

a flash memory controller connected to the plurality of memory devices in a multi-drop architecture, the flash memory controller comprising a data storage;

the memory system configured to use at least one page buffer as a cache by;

a) the flash memory controller outputting a command and an enable signal for designating one of the plurality of designated memory devices, and data from the data storage of the memory controller, the command instructing the designated memory device to temporarily store the outputted data in the page buffer of the designated device;

b) in response to the command and the enable signal, the designated memory device temporarily storing the outputted data in the page buffer of the designated device; and

repeating a) and b) to store further data from the data storage until no more temporary storage for data is needed,

wherein the command that instructs the designated memory device to temporarily store the outputted data in the page buffer of the designated device contains an operation code that is distinct from an operation code of a command used to store data in the flash memory cells of a designated memory device.

28. The memory system of claim 27 wherein the operation code is for a burst data load.

29. The memory system of claim 27 wherein:

the flash memory controller outputting the command and the enable signal comprises sending the enable signal on a dedicated connection to the designated memory device.