Memory management among levels of cache in a memory hierarchy
First Claim
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1. A method of memory management among levels of cache in a memory hierarchy in a computer with a processor operatively coupled through two or more levels of cache to a main random access memory, caches closer to the processor in the hierarchy characterized as higher in the hierarchy, the method comprising:
- identifying a line in a first cache that is preferably retained in the first cache upon an access of the line in the first cache, the first cache backed up by at least one cache lower in the memory hierarchy, the lower cache implementing a least recently used type (‘
LRU-type’
) cache line replacement policy;
wherein the method is implemented on a network on chip (‘
NOC’
), the NOC comprising integrated processor (‘
IP’
) blocks, routers, memory communications controllers, and network interface controller, each IP block adapted to a router through a memory communications controller and a network interface controller, each memory communications controller controlling communication between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers, wherein each router implements a plurality of virtual communications channels, the virtual communications channels characterized by different communication types.
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Abstract
Methods, apparatus, and product for memory management among levels of cache in a memory hierarchy in a computer with a processor operatively coupled through two or more levels of cache to a main random access memory, caches closer to the processor in the hierarchy characterized as higher in the hierarchy, including: identifying a line in a first cache that is preferably retained in the first cache, the first cache backed up by at least one cache lower in the memory hierarchy, the lower cache implementing an LRU-type cache line replacement policy; and updating LRU information for the lower cache to indicate that the line has been recently accessed.
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Citations
15 Claims
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1. A method of memory management among levels of cache in a memory hierarchy in a computer with a processor operatively coupled through two or more levels of cache to a main random access memory, caches closer to the processor in the hierarchy characterized as higher in the hierarchy, the method comprising:
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identifying a line in a first cache that is preferably retained in the first cache upon an access of the line in the first cache, the first cache backed up by at least one cache lower in the memory hierarchy, the lower cache implementing a least recently used type (‘
LRU-type’
) cache line replacement policy;wherein the method is implemented on a network on chip (‘
NOC’
), the NOC comprising integrated processor (‘
IP’
) blocks, routers, memory communications controllers, and network interface controller, each IP block adapted to a router through a memory communications controller and a network interface controller, each memory communications controller controlling communication between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers, wherein each router implements a plurality of virtual communications channels, the virtual communications channels characterized by different communication types. - View Dependent Claims (2, 3, 4, 5)
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6. An apparatus for memory management among levels of cache in a memory hierarchy in a computer with a processor operatively coupled through two or more levels of cache to a main random access memory, caches closer to the processor in the hierarchy characterized as higher in the hierarchy, the apparatus comprising a computer processor, a computer memory operatively coupled to the computer processor, the computer memory having disposed within it computer program instructions capable of:
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identifying a line in a first cache that is preferably retained in the first cache upon an access of the line in the first cache, the first cache backed up by at least one cache lower in the memory hierarchy, the lower cache implementing a least recently used type (‘
LRU-type’
) cache line replacement policy; andwherein the apparatus further comprises a network on chip (‘
NOC’
), the NOC comprising integrated processor (‘
IP’
) blocks, routers, memory communications controllers, and network interface controller, each IP block adapted to a router through a memory communications controller and a network interface controller, each memory communications controller controlling communication between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers, wherein each router implements a plurality of virtual communications channels, the virtual communications channels characterized by different communication types. - View Dependent Claims (7, 8, 9, 10)
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11. A computer program product for memory management among levels of cache in a memory hierarchy in a computer with a processor operatively coupled through two or more levels of cache to a main random access memory, caches closer to the processor in the hierarchy characterized as higher in the hierarchy, the computer program product disposed in a non-transitory computer readable, recordable medium, the computer program product comprising computer program instructions capable of:
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identifying a line in a first cache that is preferably retained in the first cache upon an access of the line in the first cache, the first cache backed up by at least one cache lower in the memory hierarchy, the lower cache implementing a least recently used type (‘
LRU-type’
) cache line replacement policy; andwherein the computer program instructions are executed on a network on chip (‘
NOC’
), the NOC comprising integrated processor (‘
IP’
) blocks, routers, memory communications controllers, and network interface controller, each IP block adapted to a router through a memory communications controller and a network interface controller, each memory communications controller controlling communication between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers, wherein each router implements a plurality of virtual communications channels, the virtual communications channels characterized by different communication types. - View Dependent Claims (12, 13, 14, 15)
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Specification
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Current AssigneeInternational Business Machines Corporation
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Original AssigneeInternational Business Machines Corporation
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InventorsHeil, Timothy H., Shearer, Robert A.
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Primary Examiner(s)Chery, Mardochee
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Application NumberUS13/778,862Publication NumberTime in Patent Office573 DaysField of Search710/136, 710/119, 710/162, 710/143, 710/E12.016US Class Current711/118CPC Class CodesG06F 12/122 of the least frequently use...G06F 12/128 adapted to multidimensional...
