Inverse chip connector

• US 8,846,445 B2
• Filed: 06/20/2011
• Issued: 09/30/2014
• Est. Priority Date: 06/14/2005
• Status: Active Grant

• Current Assignee: Cufer Asset Ltd LLC (Intellectual Ventures LLC)
• Original Assignee: Cufer Asset Ltd LLC (Intellectual Ventures LLC)
• Inventors: Trezza, John
• Primary Examiner(s): Sandvik, Benjamin
• Assistant Examiner(s): Cruz, Leslie Pilar
• Application Number:
  US13/164,193
• Publication Number:
  US 20110250722A1
• Time in Patent Office: 1,198 Days
• Field of Search: None
• US Class Current: 438/107
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2221/68363 used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: H01L 2221/68368 used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
• CPC Class Codes: H01L 2223/6616 Vertical connections, e.g. vias
• CPC Class Codes: H01L 2223/6622 Coaxial feed-throughs in active or passive substrates
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/114 by blanket deposition of the material of the bump connector
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/116 by patterning a pre-deposited material treatment of parts prior to assembly of the devices H01L21/48
• CPC Class Codes: H01L 2224/11912 the bump being used as a mask for patterning other parts
• CPC Class Codes: H01L 2224/13012 in top view
• CPC Class Codes: H01L 2224/13021 the bump connector being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/1308 being stacked
• CPC Class Codes: H01L 2224/13082 Two-layer arrangements
• CPC Class Codes: H01L 2224/13083 Three-layer arrangements
• CPC Class Codes: H01L 2224/13084 : Four-layer arrangements
• CPC Class Codes: H01L 2224/13099 : Material
• CPC Class Codes: H01L 2224/13111 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13144 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13166 : Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/13184 : Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/1358 : being stacked
• CPC Class Codes: H01L 2224/136 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13609 : Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/16146 : the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16237 : the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/24226 : the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 2224/45111 : Tin (Sn) as principal constituent
• CPC Class Codes: H01L 2224/75 : Apparatus for connecting with bump connectors or layer connectors
• CPC Class Codes: H01L 2224/75305 : comprising protrusions
• CPC Class Codes: H01L 2224/81001 : involving a temporary auxiliary member not forming part of the bonding apparatus
• CPC Class Codes: H01L 2224/81011 : Chemical cleaning, e.g. etching, flux
• CPC Class Codes: H01L 2224/81054 : Composition of the atmosphere
• CPC Class Codes: H01L 2224/81136 : involving guiding structures, e.g. spacers or supporting members
• CPC Class Codes: H01L 2224/81193 : wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81203 : Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/81204 : with a graded temperature profile
• CPC Class Codes: H01L 2224/81825 : Solid-liquid interdiffusion
• CPC Class Codes: H01L 2224/81894 : Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
• CPC Class Codes: H01L 2224/83102 : using surface energy, e.g. capillary forces
• CPC Class Codes: H01L 2224/92125 : the second connecting process involving a layer connector
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06524 : Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06531 : Non-galvanic coupling, e.g. capacitive coupling
• CPC Class Codes: H01L 2225/06534 : Optical coupling
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06555 : Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06589 : Thermal management, e.g. cooling
• CPC Class Codes: H01L 2225/06593 : Mounting aids permanently on device; arrangements for alignment use of temporary supports H01L21/6835
• CPC Class Codes: H01L 2225/06596 : Structural arrangements for testing testing or measuring during manufacture or treatment H01L22/00; testing electrical properties or locating electrical faults G01R31/00
• CPC Class Codes: H01L 23/427 : Cooling by change of state, e.g. use of heat pipes by liquefied gas H01L23/445
• CPC Class Codes: H01L 23/48 : Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/488 : consisting of soldered or bonded constructions bump connectors H01L24/01
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/552 : Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/66 : High-frequency adaptations
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/75 : Apparatus for connecting with bump connectors or layer connectors
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01002 : Helium [He]
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01007 : Nitrogen [N]
• CPC Class Codes: H01L 2924/01012 : Magnesium [Mg]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01025 : Manganese [Mn]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01051 : Antimony [Sb]
• CPC Class Codes: H01L 2924/01052 : Tellurium [Te]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01S 2301/176 : Specific passivation layers on surfaces other than the emission facet
• CPC Class Codes: H01S 5/02345 : Wire-bonding
• CPC Class Codes: H01S 5/0237 : by soldering
• CPC Class Codes: H01S 5/0422 : with n- and p-contacts on the same side of the active layer
• CPC Class Codes: H01S 5/0425 : Electrodes, e.g. characterised by the structure
• CPC Class Codes: H01S 5/04254 : characterised by the shape
• CPC Class Codes: H01S 5/04257 : having positive and negative electrodes on the same side of the substrate
• CPC Class Codes: H01S 5/183 : having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
• CPC Class Codes: H01S 5/18308 : having a special structure for lateral current or light confinement

Abstract

A system for connecting a first chip to a second chip having a post on the first chip having a first metallic material, a recessed wall within the second chip and defining a well within the second chip, a conductive diffusion layer material on a surface of the recessed wall within the well, and a malleable electrically conductive material on the post, the post being dimensioned for insertion into the well such that the malleable electrically conductive material will deform within the well and, upon heating to at least a tack temperature for the malleable, electrically conductive material, will form an electrically conductive tack connection with the diffusion layer to create an electrically conductive path between the first chip and the second chip.

Claims

1. A method comprising:

aligning an electrically-conductive post on a first chip with an electrically-conductive well in a second chip, wherein a first electrically-conductive material is disposed over the electrically-conductive post, wherein the first electrically-conductive material is more malleable than the electrically-conductive post, and wherein the first electrically-conductive material has a size that is larger than an opening of the electrically-conductive well; and

inserting the electrically-conductive post into the electrically-conductive well to cause the first electrically-conductive material to deform and create an electrically-conductive path between the first chip and the second chip.

2. The method of claim 1, wherein the electrically-conductive well comprises an electrically-conductive diffusion layer disposed on a surface of the electrically-conductive well, and wherein the first electrically-conductive material is more malleable than the electrically-conductive diffusion layer.

3. The method of claim 2, wherein the electrically-conductive post, the first electrically-conductive material, and the electrically-conductive diffusion layer completely fill the electrically-conductive well after said inserting the electrically-conductive post into the electrically-conductive well.

4. The method of claim 1, wherein the electrically-conductive post comprises a height from a surface of the first chip and a width across an end of the electrically-conductive post, and wherein the width across the end of the electrically-conductive post is larger than a corresponding width of the electrically-conductive well prior to said inserting the electrically-conductive post into the electrically-conductive well.

5. The method of claim 1, wherein the electrically-conductive well has a shape and dimension at an outer surface of the electrically-conductive well configured to assist with alignment of the electrically-conductive post during said inserting the electrically-conductive post into the electrically-conductive well.

6. The method of claim 5, wherein walls of the electrically-conductive well are angled outward from a center of the electrically-conductive well at a substantially constant angle such that a diameter of the electrically-conductive well at the outer surface of the second chip is greater than a diameter of the electrically-conductive well at an inner portion of the second chip.

7. The method of claim 1, wherein the electrically-conductive well substantially surrounds a portion of a partially-filled via.

8. The method of claim 1, wherein the first electrically-conductive material comprises a metal having a melting point of less than approximately 1000 degrees Celsius.

9. The method of claim 1, wherein the first electrically-conductive material comprises at least one of tin, indium, lead, bismuth, aluminum, zinc, magnesium, or an alloy thereof.

10. A method comprising:

aligning a post on a first chip with a well in a second chip, wherein the well comprises a first electrically-conductive material, and wherein the post comprises a rigid electrically-conductive material and a second electrically-conductive material more malleable than both the first electrically-conductive material and the rigid electrically-conductive material; and

inserting the post into the well to cause the second electrically-conductive material to deform and create an electrically-conductive path between the first chip and the second chip,

wherein the first electrically-conductive material is disposed over a recessed wall of the well and wherein the well comprises a depth extending into the second chip and a width extending across an outer opening of the well, wherein the width extending across the outer opening of the well corresponds to a width of the post, and wherein the width of the post is larger than the corresponding width extending across the outer opening of the well prior to said inserting the post into the well.

11. The method of claim 10, wherein the recessed wall of the well is coated with a diffusion layer.

12. The method of claim 10, wherein the first electrically-conductive material is disposed over a recessed wall of the well, and wherein the second electrically-conductive material is disposed over the rigid electrically-conductive material.

13. The method of claim 10, wherein walls of the well are angled outward from a center of the well such that a diameter of the well at the outer surface is greater than a diameter of the well at an inner portion of the well.

14. The method of claim 13, wherein the diameter of the well at the outer surface is greater than a largest diameter of the post.

15. The method of claim 10, wherein the well is formed in a partially-filled via.

16. A method comprising:

aligning an electrically-conductive post on a first chip with an electrically-conductive well in a second chip, wherein a first electrically-conductive material is disposed over the electrically-conductive post, wherein the first electrically-conductive material is more malleable than the electrically-conductive post, and wherein the first electrically-conductive material has a size that is larger than an opening of the electrically-conductive well; and

inserting the electrically-conductive post into the electrically-conductive well, thereby causing the first electrically-conductive material to deform without deformation of the electrically-conductive post; and

heating the first electrically-conductive material to form an electrically-conductive connection between the first chip and the second chip.

17. The method of claim 16, wherein the electrically-conductive well comprises an electrically-conductive diffusion layer disposed on a surface of the electrically-conductive well, and wherein the first electrically-conductive material is more malleable than the electrically-conductive diffusion layer.

18. The method of claim 16, wherein the electrically-conductive well comprises a depth extending into the second chip and a width extending across an outer opening of the electrically-conductive well, wherein the width extending across the outer opening of the electrically-conductive well corresponds to a width of the electrically-conductive post, and wherein the width of the electrically-conductive post is larger than the corresponding width extending across the outer opening of the electrically-conductive well such that said inserting the electrically-conductive post into the electrically-conductive well causes the second electrically-conductive material to deform.

19. The method of claim 16, wherein walls of the electrically-conductive well are angled outward from a center of the electrically-conductive well such that a diameter of the electrically-conductive well at an outer surface of the electrically-conductive well is greater than a diameter of the electrically-conductive well at an inner portion of the electrically-conductive well.

20. The method of claim 16, wherein the electrically-conductive well substantially surrounds a portion of a partially-filled via.

21. The method of claim 16, wherein said heating is performed prior to said inserting.

22. The method of claim 16, wherein said heating is performed after said inserting.

23. The method of claim 16, wherein the first electrically-conductive material is configured to deform upon said inserting at a temperature below a melting point of the first electrically-conductive material.