Method to construct a 3D semiconductor device

• US 8,846,463 B1
• Filed: 05/24/2013
• Issued: 09/30/2014
• Est. Priority Date: 02/16/2010
• Status: Expired due to Fees

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Wurman, Zeev
• Primary Examiner(s): Booth, Richard
• Application Number:
  US13/902,606
• Time in Patent Office: 494 Days
• Field of Search: 438151-166
• US Class Current: 438/155
• CPC Class Codes: H01L 21/268 using electromagnetic radiation, e.g. laser radiation
• CPC Class Codes: H01L 21/302 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/8232 Field-effect technology
• CPC Class Codes: H01L 21/8238 Complementary field-effect transistors, e.g. CMOS
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 2224/05099 Material
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13599 Material
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/29099 Material
• CPC Class Codes: H01L 2224/29599 Material
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/4827 : Materials
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 27/0207 : Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0688 : Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/11807 : CMOS gate arrays
• CPC Class Codes: H01L 27/1203 : the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01066 : Dysprosium [Dy]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/1436 : Dynamic random-access memory [DRAM]
• CPC Class Codes: H01L 2924/1437 : Static random-access memory [SRAM]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

A method to construct a semiconductor device, the method including: forming a first mono-crystallized semiconductor layer; forming a second mono-crystallized semiconductor layer including mono-crystallized semiconductor transistors; where the second mono-crystallized semiconductor layer overlays the first mono-crystallized semiconductor layer, where the first mono-crystallized semiconductor layer includes an alignment mark and the transistors are aligned to the alignment mark, and where the first mono-crystallized semiconductor layer includes logic circuits, and connecting the logic circuits to an external device using input/output (I/O) circuits, where the input/output (I/O) circuits are constructed on the second mono-crystallized semiconductor layer.

Claims

1. A method to construct a semiconductor device, the method comprising:

forming a first layer comprising mono-crystallized semiconductor and first logic circuits;

forming a second layer comprising a mono-crystallized semiconductor layer, said second layer overlying said first logic circuits;

forming transistors on said second layer;

wherein said forming transistors comprises a lithography step, said lithography step comprises an alignment to said first layer, and

connecting said first logic circuits to an external device using input/output (I/O) circuits, said input/output (I/O) circuits are constructed on said second mono-crystallized semiconductor layer.

2. The method according to claim 1,

wherein said first logic circuits comprise copper or aluminum interconnect, and

wherein a plurality of said transistors are connected to form second logic circuits.

3. The method according to claim 1,

wherein said first logic circuits comprises copper or aluminum interconnect, and

wherein at least one of said transistors is a horizontally oriented transistor.

4. The method according to claim 1, further comprising:

etching at least a portion of said transistors in a customization step of a generic structure.

5. The method according to claim 1,

wherein said semiconductor device comprises a circuit that provides a wireless connection to a device that is external to said semiconductor device.

6. The method according to claim 1,

wherein said forming transistors comprises optical annealing.

7. The method according to claim 1,

wherein said forming transistors comprises gate replacement.

8. A method to construct a semiconductor device, the method comprising:

forming a first layer comprising mono-crystallized semiconductor and first logic circuits;

forming a second layer comprising a mono-crystallized semiconductor layer, said second layer overlying said first logic circuits;

forming transistors on said second layer;

wherein said forming transistors comprises a lithography step, said lithography step comprises an alignment to said first layer, and

connecting said first logic circuits to an external device using input/output (I/O) circuits, said input/output (I/O) circuits are constructed on said second mono-crystallized semiconductor layer,

wherein said input/output (I/O) circuits comprise a SerDes circuit.

9. The method according to claim 8,

wherein said first logic circuits comprise copper or aluminum interconnect, and

wherein a plurality of said transistors are connected to form second logic circuits.

10. The method according to claim 8,

wherein said semiconductor device comprises a circuit that provides a wireless connection to a device that is external to said semiconductor device.

11. The method according to claim 8, further comprising:

etching at least a portion of said transistors in a customization step of a generic structure.

12. The method according to claim 8, wherein said connecting comprises applying at least one Through Silicon Via (TSV).

13. The method according to claim 8,

wherein said forming transistors comprises optical annealing.

14. The method according to claim 8,

wherein said forming transistors comprises gate replacement.

15. A method to construct a semiconductor device, the method comprising:

forming a first layer comprising mono-crystallized semiconductor and first logic circuits;

forming a second layer comprising a mono-crystallized semiconductor layer, said second layer overlying said first logic circuits;

forming transistors on said second layer;

wherein said forming transistors comprises a lithography step, said lithography step comprises an alignment to said first layer,

wherein said transistors are connected to form second logic circuits, and

wherein said second logic circuits comprise a scan chain.

16. The method according to claim 15,

wherein said first logic circuits comprise copper or aluminum interconnect.

17. The method according to claim 15,

wherein said first logic circuits comprises copper or aluminum interconnect, and

wherein at least one of said transistors is a horizontally oriented transistor.

18. The method according to claim 15, further comprising:

etching at least a portion of said transistors in a customization step of a generic structure.

19. The method according to claim 15,

wherein said semiconductor device comprises a circuit that provides a wireless connection to an external device.

20. The method according to claim 15, further comprising:

connecting said first logic circuits to an external device using input/output (I/O) circuits, said input/output (I/O) circuits are constructed on said second mono-crystallized semiconductor layer.

21. The method according to claim 15,

wherein said forming transistors comprises gate replacement.