Fabrication method of trenched power semiconductor device with source trench
First Claim
1. A fabrication method of a trenched power semiconductor device with a source trench, comprising the steps of:
- providing a base;
forming at least two gate trenches in the base;
forming a first dielectric layer to line the inner surfaces of the gate trenches;
forming a first polysilicon structure in the gate trenches lining with the first dielectric layer;
forming an interlayer dielectric structure on the first polysilicon structure to define at least a source trench;
forming the source trench between the two neighboring gate trenches;
forming a second dielectric layer to line the inner surfaces of the source trench;
forming a second polysilicon structure in a lower portion of the source trench lining with the second dielectric layer;
forming a body region between the gate trenches, wherein the depth of the source trench is greater than the depth of the body region;
forming a source region between the gate trenches;
removing a portion of the second dielectric layer to expose the source region and the body region; and
filling a conductive structure in the source trench for electrically connecting the second polysilicon structure, the body region, and the source region,wherein the step of forming the source trench comprises;
forming a spacer on a side surface of the interlayer dielectric structure; and
etching the exposed body region to form the source trench,wherein prior to the formation of the spacer, further comprising the step of forming a heavily doped region in the body region by using the interlayer dielectric structure as an implantation mask.
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Accused Products
Abstract
A fabrication method of a trenched power semiconductor device with source trench is provided. Firstly, at least two gate trenches are formed in a base. Then, a dielectric layer and a polysilicon structure are sequentially formed in the gate trench. Afterward, at least a source trench is formed between the neighboring gate trenches. Next, the dielectric layer and a second polysilicon structure are sequentially formed in the source trench. The second polysilicon structure is located in a lower portion of the source trench. Then, the exposed portion of the dielectric layer in the source trench is removed to expose a source region and a body region. Finally, a conductive structure is filled into the source trench to electrically connect the second polysilicon structure, the body region, and the source region.
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Citations
20 Claims
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1. A fabrication method of a trenched power semiconductor device with a source trench, comprising the steps of:
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providing a base; forming at least two gate trenches in the base; forming a first dielectric layer to line the inner surfaces of the gate trenches; forming a first polysilicon structure in the gate trenches lining with the first dielectric layer; forming an interlayer dielectric structure on the first polysilicon structure to define at least a source trench; forming the source trench between the two neighboring gate trenches; forming a second dielectric layer to line the inner surfaces of the source trench; forming a second polysilicon structure in a lower portion of the source trench lining with the second dielectric layer; forming a body region between the gate trenches, wherein the depth of the source trench is greater than the depth of the body region; forming a source region between the gate trenches; removing a portion of the second dielectric layer to expose the source region and the body region; and filling a conductive structure in the source trench for electrically connecting the second polysilicon structure, the body region, and the source region, wherein the step of forming the source trench comprises; forming a spacer on a side surface of the interlayer dielectric structure; and etching the exposed body region to form the source trench, wherein prior to the formation of the spacer, further comprising the step of forming a heavily doped region in the body region by using the interlayer dielectric structure as an implantation mask. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A fabrication method of a trenched power semiconductor device with a source trench, comprising the steps of:
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providing a base; forming at least two gate trenches in the base; forming a first dielectric layer to line the inner surfaces of the gate trenches; forming a first polysilicon structure in the gate trenches lining with the first dielectric layer; forming an interlayer dielectric structure on the first polysilicon structure to define at least a source trench; forming the source trench between the two neighboring gate trenches; forming a second dielectric layer to line the inner surfaces of the source trench; forming a second polysilicon structure in a lower portion of the source trench lining with the second dielectric layer; forming a body region between the gate trenches, wherein the depth of the source trench is greater than the depth of the body region; forming a source region between the gate trenches; removing a portion of the second dielectric layer to expose the source region and the body region; and filling a conductive structure in the source trench for electrically connecting the second polysilicon structure, the body region, and the source region, wherein the step of forming the source trench comprises; forming a spacer on a side surface of the interlayer dielectric structure; and etching the exposed body region to form the source trench wherein the spacer is removed in the step of removing the portion of the second dielectric layer to expose the source region and the body region. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification