Process of forming through-silicon via structure

• US 8,846,523 B2
• Filed: 04/01/2013
• Issued: 09/30/2014
• Est. Priority Date: 06/12/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wu, Weng-Jin, Chiou, Wen-Chih, Lin, Yung-Chi
• Primary Examiner(s): SUN, YU-HSI DAVID
• Application Number:
  US13/854,230
• Publication Number:
  US 20130224909A1
• Time in Patent Office: 547 Days
• Field of Search: 257/773, 257/E21.577, 257/E21.585, 438/629
• US Class Current: 438/629
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0554 External layer
• CPC Class Codes: H01L 2224/0555 Shape
• CPC Class Codes: H01L 2224/0556 Disposition
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/525 with adaptable interconnections
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 Fully indexed content
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01012 Magnesium [Mg]
• CPC Class Codes: H01L 2924/01025 : Manganese [Mn]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

In a process, an opening is formed to extend from a front surface of a semiconductor substrate through at least a part of the semiconductor substrate. A metal seed layer is formed on a sidewall of the opening. A metal silicide layer is formed on at least one portion of the metal seed layer. A metal layer is formed on the metal silicide layer and the metal seed layer to fill the opening.

Claims

1. A process, comprising:

forming an opening extending from a front surface of a semiconductor substrate through at least a part of the semiconductor substrate;

forming a metal seed layer on a sidewall of the opening;

forming a metal silicide layer on at least one portion of the metal seed layer; and

forming a metal layer on the metal silicide layer and the metal seed layer to fill the opening,

wherein the metal seed layer comprises a bottom portion adjacent to a bottom of the opening, and the metal silicide layer is not formed on the bottom portion of the metal seed layer.

2. The process of claim 1, wherein the metal silicide layer comprises copper.

3. The process of claim 1, wherein the metal layer comprises copper, and the metal seed layer comprises copper.

4. The process of claim 1, further comprising:

forming a barrier layer lining the opening before forming the metal seed layer, wherein barrier layer comprises at least one selected from the group consisting of TaN, Ta, TiN, and Ti.

5. The process of claim 4, further comprising:

forming a passivation layer lining the opening before forming the barrier layer.

6. The process of claim 5, wherein the passivation layer comprises silicon oxide.

7. The process of claim 1, further comprising:

performing a thinning process on a back surface of the semiconductor substrate to expose an end of the metal layer.

8. The process of claim 7, further comprising:

stacking a semiconductor component on the back surface of the semiconductor substrate, the semiconductor component electrically connected to the exposed end of the metal layer.

9. A process, comprising:

forming an opening extending from a front surface of a semiconductor substrate through at least a part of the semiconductor substrate;

forming a metal seed layer on a sidewall of the opening;

forming a metal silicide layer on the metal seed layer, wherein a bottom of the opening is free of the metal silicide layer; and

forming a metal layer on the metal silicide layer and the metal seed layer to fill the opening.

10. The process of claim 9, further comprising, before forming the metal seed layer:

forming a passivation layer lining the opening; and

then

forming a barrier layer over the passivation layer.

11. The process of claim 10, wherein the semiconductor substrate includes an integrated circuit (IC) component formed on the front surface, the process further comprising:

forming an interlayer dielectric (ILD) layer over the front surface of the semiconductor substrate; and

forming a contact plug in the ILD layer, the contact plug electrically coupled to the IC component,

wherein the opening is formed through the ILD layer.

12. The process of claim 11, further comprising:

performing a thinning process on a back surface of the semiconductor substrate to expose an end of the metal layer; and

stacking a semiconductor component on the back surface of the semiconductor substrate, the semiconductor component electrically connected to the exposed end of the metal layer.

13. The process of claim 9, further comprising:

forming a backside dielectric layer over a back surface of the semiconductor substrate; and

forming an external contact on the backside dielectric layer.

14. The process of claim 13, wherein the external contact comprises at least one selected from the group consisting of a solder bump and a copper-containing bump.

15. A process, comprising:

forming an opening extending from a front surface of a semiconductor substrate to at least a part of the semiconductor substrate, wherein the opening has an aspect ratio greater than 5;

forming a metal seed layer in the opening, wherein the metal seed layer comprises a sidewall portion adjacent to the sidewall of the opening, and a bottom portion adjacent to the bottom of the opening;

forming a metal silicide layer on at least a part of the sidewall portion of the metal seed layer; and

plating a metal layer on the metal silicide layer and the metal seed layer to fill the opening,

wherein the metal silicide layer is not formed on the bottom portion of the metal seed layer.

16. The process of claim 15, wherein each of the metal seed layer, the metal silicide layer and the metal layer comprises copper.

17. The process of claim 15, further comprising:

forming a barrier layer lining the opening before forming the metal seed layer.

18. The process of claim 17, further comprising:

forming a passivation layer lining the opening before forming the barrier layer.

19. The process of claim 15, further comprising:

performing a thinning process on a back surface of the semiconductor substrate to expose the metal layer.