Direct contact in trench with three-mask shield gate process

• US 8,847,306 B2
• Filed: 01/04/2012
• Issued: 09/30/2014
• Est. Priority Date: 09/23/2009
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Tai, Sung-Shan, Yilmaz, Hamza, Bhalla, Anup, Chang, Hong, Chen, John
• Primary Examiner(s): YUSHIN, NIKOLAY K
• Application Number:
  US13/343,666
• Publication Number:
  US 20120098059A1
• Time in Patent Office: 1,000 Days
• Field of Search: 257/330, 257/328, 257/334, 257/E29.262, 257/E21.19, 438/270, 438/586, 438/589, 438/629
• US Class Current: 257/330
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor substrate may be etched to form trenches with three different widths. A first conductive material is formed at the bottom of the trenches. A second conductive material separated by an insulator is formed over the first conductive material. A first insulator layer is formed on the trenches. A body layer is formed in the substrate. A source is formed in the body layer. A second insulator layer is formed on the trenches and source. Source and gate contacts are formed through the second insulator layer. Source and gate metal are formed on the second insulator layer. This abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Claims

1. A method for making a shield gate trench semiconductor device, comprising:

a) etching a semiconductor substrate to form trenches TR1, TR2 and TR3 with three widths Wl, W2 and W3, respectively, wherein the trench TR3 is widest and deepest and the width W3 of the trench TR3 depends on a depth D2 of the trench TR2, wherein the semiconductor substrate includes an epitaxial layer over a heavily doped substrate and wherein the trench TR3 extends into the heavily doped substrate and the trenches TR1 and TR2 do not;

b) forming first conductive material at the bottom of the trenches TR1, TR2 and TR3 to form a source electrode;

c) forming a second conductive material over the first conductive material in the trenches TR1 and TR2 to form a gate electrode, wherein the first and second conductive materials are separated from each other and from the semiconductor substrate by an insulator material;

d) depositing a first insulator layer on top of the trenches TR1, TR2 and TR3, wherein a top portion of the trench TR3 is filled up with the insulator;

e) forming a body layer in a top portion of the substrate;

f) forming a source layer in a top portion of the body layer;

g) applying a second insulator layer on top of the trenches TR1, TR2 and TR3 and the source;

h) forming a source electrode contact in trench TR3, a gate electrode contact in trench TR2, and a source/body contact to the semiconductor substrate; and

i) forming source metal and gate metal on top of the second insulator layer.

2. The method of claim 1 wherein k) comprises:

depositing a metal layer on top of the second insulator layer;

applying a metal mask as the third mask on top of the metal layer; and

etching the metal layer to form the gate metal and the source metal through the metal mask.

3. The method of claim 1, wherein a) comprises:

depositing an oxide layer on top of the semiconductor substrate; and

patterning the oxide layer with the first mask to form a hard mask.

4. The method of claim 1 wherein the W1 is about 0.3 micron to 0.5 micron;

W2 is about 0.6 micron to 0.9 micron; and

W3 is about 1.2 microns to 2.0 microns.

5. The method of claim 1, wherein a ratio W3/W2 is about 1.5 to 3.

6. The method of claim 1, wherein a ratio W3/D2 is about 1.1 to 1.3.

7. The method of claim 1 wherein c) comprises:

forming an oxide layer on sidewall of the trenches TR1, TR2 and TR3;

in-situ depositing the first conductive material into the trenches TR1, TR2 and TR3; and

etching back the first conductive material.

8. The method of claim 7 wherein a thickness of the oxide layer is about 1500 Angstroms to 2500 Angstroms.

9. A semiconductor device comprising:

a plurality of shield gate trench field effect transistors, each of which includes a conductive shield electrode and a conductive gate electrode formed in a trench TR1;

a trench TR3 having a conductive shield electrode formed in a bottom of the trench but not having a conductive gate electrode;

a trench TR2 having a conductive gate electrode formed over a conductive shield electrode, wherein the trench TR3 is wider and deeper than the trench TR2;

one or more vertical shield electrode contacts configured to directly electrically connect the conductive shield electrode in trench TR3 to a source metal; and

vertical gate contacts configured to direct electrically connected the conductive gate electrode in trench TR2 to a gate metal,

wherein the trench TR3 is wider and deeper than the trench TR2, wherein the shield gate field effect transistors are formed in an epitaxial layer over a heavily doped substrate, and wherein the trench TR3 extends into the heavily doped substrate and the trenches TR1 and TR2 do not.

10. The semiconductor device of claim 9 wherein the trench TR2 is wider and deeper than the trench TR1.

11. The semiconductor device of claim 9, wherein outermost ring of the trench TR3 also acts as a guard ring for the termination area.

12. A semiconductor device comprising:

a plurality of shield gate trench field effect transistors, each of which includes a conductive shield electrode and a conductive gate electrode formed in a trench TR1;

a trench TR3 having a conductive shield electrode formed in a bottom of the trench but not having a conductive gate electrode;

a trench TR2 having a conductive gate electrode formed over a conductive shield electrode, wherein the trench TR2 is wider and deeper than the trench TR1 and wherein the trench TR3 is wider and deeper than the trench TR2;

one or more vertical shield electrode contacts configured to directly electrically connect the conductive shield electrode in trench TR3 to a source metal; and

vertical gate contacts configured to direct electrically connected the conductive gate electrode in trench TR2 to a gate metal.

13. The semiconductor device of claim 12, wherein outermost ring of the trench TR3 also acts as a guard ring for the termination area.