Power semiconductor devices, methods, and structures with embedded dielectric layers containing permanent charges

• US 8,847,307 B2
• Filed: 12/04/2012
• Issued: 09/30/2014
• Est. Priority Date: 04/13/2010
• Status: Active Grant

• Current Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Darwish, Mohamed N., Zeng, Jun, Blanchard, Richard A.
• Primary Examiner(s): TRAN, MINH LOAN
• Application Number:
  US13/693,714
• Publication Number:
  US 20140054741A1
• Time in Patent Office: 665 Days
• Field of Search: 257/330, 257/492, 257/493, 257/E29.012, 257/E29.201
• US Class Current: 257/330
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0611 for increasing or controlling the breakdown voltage of reverse biased devices H01L29/0661 takes precedence
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0873 Drain regions
• CPC Class Codes: H01L 29/0882 Disposition
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/8611 Planar PN junction diodes

Abstract

Power devices using refilled trenches with permanent charge at or near their sidewalls. These trenches extend vertically into a drift region.

Claims

1. A semiconductor power device, comprising:

an array of active device cells, including both an upper array of current-controlling structures, and a lower array of permanently charged trenches within a semiconducting drift region;

said trenches individually containing permanent electrostatic charge at or near sidewalls thereof; and

a transitional structure surrounding said array, said transitional structure including at least some trenches which are fabricated in the same steps as said trenches in said array, but which have smaller maximum width, and a different ratio of charge density between upper and lower portions of the walls of said trenches.

2. The device of claim 1, wherein said trenches and said current-controlling structure have different respective pitches.

3. The device of claim 1, wherein permanent electrostatic charge is present at sidewalls of said trenches.

4. The device of claim 1, wherein said trenches are lined with a dielectric layer which includes immobile ions.

5. The device of claim 1, wherein the device is unipolar, and said first source/drain region is a source.

6. The device of claim 1, wherein the device is a diode, and said first source/drain region is a cathode.

7. The device of claim 1, wherein said semiconductor mass is a Group IV semiconductor.

8. The device of claim 1, wherein said mass is a die of crystalline semiconducive material.

9. The device of claim 1, wherein said trench-filling material is a semiconductive material.

10. The device of claim 1, wherein said trench-filling material is made of the same semiconductive material as said drift region.

11. The device of claim 1, wherein said trench-filling material is a doped crystalline semiconductive material.

12. The device of claim 1, wherein said trench-filling material is a semiconductive material grown by selective epitaxy.

13. The device of claim 1, wherein said trench-filling material is a semiconductive material which has approximately the same doping as said drift region.

14. The device of claim 1, wherein said trenches are generally shaped as linear slots, and said trench-filling material is semiconductive, and wherein the volumetric doping density of said trench-filling material, times the width of said trenches, is approximately equal to the volumetric doping density of said drift region, times the distance between adjacent ones of said trenches.

15. The device of claim 1, wherein said second source/drain region is connected as an anode.

16. A semiconductor voltage blocking structure, comprising:

a layered semiconductor structure which includes at least an upper semiconductor portion and a lower semiconductor portion;

said upper portion including a first anode/cathode diffusion, and said lower portion including a drift region;

said drift region being electrically interposed in series between said first anode/cathode region, and a second anode/cathode region at a second surface of said layered semiconductor structure; and

trenches extending down into said layered semiconductor structure, at least one of said trenches being at least partially filled with a semiconductive trench-filling material which conducts current in parallel with portions of said lower portion outside said trench;

wherein said trenches are lined with a dielectric layer which has been loaded with immobile cesium ions.

17. The voltage blocking structure of claim 16, wherein said layered semiconductor structure consists essentially of silicon.

18. The voltage blocking structure of claim 16, wherein said lower portion is a crystalline semiconductor substrate, and said upper portion is an epitaxial layer on said substrate.

19. A method for operating a power device which switches between an ON state and an OFF state, comprising:

controlling ON-state current by use of a current-controlling structure at a first surface of a semiconductor mass;

said ON-state current flowing through a drift region, to provide a controllable electrical connection between a first source/drain region, at said first surface, and a second source/drain region which is not otherwise connected to said first source/drain region; and

blocking current, in the OFF state, using said drift region in conjunction said current-controlling structure;

wherein bottomless trenches extend into said drift region, and at least some said trenches are at least partially filled with a trench-filling material which is not an insulator, and which is electrically connected to said second source/drain region;

wherein said at least some trenches individually contain permanent electrostatic charge at or near sidewalls thereof.