Metal-insulator-metal capacitors with high capacitance density

• US 8,847,354 B2
• Filed: 01/24/2013
• Issued: 09/30/2014
• Est. Priority Date: 12/15/2010
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Abou-Khalil, Michel J., Gauthier, Robert J. Jr., Lee, Tom C., Li, Junjun, Mitra, Souvick, Putnam, Christopher S., Stamper, Anthony K.
• Primary Examiner(s): Jackson, Jr., Jerome
• Assistant Examiner(s): Budd, Paul
• Application Number:
  US13/749,146
• Publication Number:
  US 20130134557A1
• Time in Patent Office: 614 Days
• Field of Search: 257/301, 257/306, 257/532, 257/E21.012, 257/E21.016, 257/E21.018, 257/310
• US Class Current: 257/532
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 28/82 with an enlarged surface, e.g. formed by texturisation
• CPC Class Codes: H01L 28/90 having vertical extensions
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Metal-insulator-metal (MIM) capacitors and methods for fabricating MIM capacitors. The MIM capacitor includes an interlayer dielectric (ILD) layer with apertures each bounded by a plurality of sidewalls and each extending from the top surface of the ILD layer into the first interlayer dielectric layer. A layer stack, which is disposed on the sidewalls of the apertures and the top surface of the ILD layer, includes a bottom conductive electrode, a top conductive electrode, and a capacitor dielectric between the bottom and top conductive electrodes.

Claims

1. A metal-insulator-metal (MIM) capacitor comprising:

a first interlayer dielectric (ILD) layer having a top surface, a plurality of apertures, a first surface area with a perimeter surrounding the apertures, and a second surface area surrounding the first surface area, each aperture including a plurality of sidewalls that extend from the top surface of the first ILD layer into the first ILD layer;

a conformal dielectric layer on the top surface of the first ILD layer and the sidewalls of the apertures; and

a layer stack on the conformal dielectric layer, the layer stack including a first electrode and a capacitor dielectric layer, and the first electrode separated from the first ILD layer by the conformal dielectric layer.

2. The MIM capacitor of claim 1 further comprising:

a second interlayer dielectric (ILD) layer having a top surface on which the first ILD layer is formed, each aperture extending through the first ILD layer from the top surface of the first ILD layer to the top surface of the second ILD layer so that a depth of the apertures is approximately equal to a layer thickness of the first ILD layer.

3. The MIM capacitor of claim 2 wherein the second ILD layer includes a wiring feature exposed along the top surface of the second ILD layer, at least one of the apertures lands on the wiring feature, and the first electrode contacts the wiring feature.

4. The MIM capacitor of claim 1 wherein the apertures have an elongated geometry that partitions the first ILD layer into a plurality of via bars.

5. The MIM capacitor of claim 1 wherein the first ILD layer comprises a dielectric material, and the apertures are square or rectangular such that the dielectric material is partitioned by the apertures into a grid of intersecting lines.

6. The MIM capacitor of claim 1 wherein the layer stack further includes a second electrode separated from the first electrode by the capacitor dielectric layer.

7. The MIM capacitor of claim 1 wherein the conformal dielectric layer comprises silicon dioxide (SiO₂), silicon nitride (Si₃N₄), or aluminum oxide (Al₂O₃).