Optimization methodology and apparatus for wide-swing current mirror with wide current range

• US 8,847,572 B2
• Filed: 07/20/2012
• Issued: 09/30/2014
• Est. Priority Date: 04/13/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Tsai, Tsung-Hsien
• Primary Examiner(s): Hiltunen, Thomas J
• Application Number:
  US13/554,043
• Publication Number:
  US 20130271106A1
• Time in Patent Office: 802 Days
• Field of Search: 323/315, 323/317
• US Class Current: 323/317
• CPC Class Codes: G05F 3/262 using field-effect transistors only

Abstract

A current mirror circuit includes an input portion configured to conduct a bias current, and a first current source circuit coupled to the input portion and configured to generate the bias current, and vary the bias current over a range of currents based on a first group of weightings associated therewith. The current mirror circuit also includes an output portion configured to conduct an operational current, wherein the output portion is coupled to the input portion, and a second current source circuit coupled to the output portion and configured to generate the operational current, and vary the operational current over a range of currents based on a second group of weightings associated therewith. The first group of weightings and the second group of weightings are different.

Claims

1. A current mirror circuit, comprising:

a first transistor having a drain terminal coupled to a gate terminal thereof, and configured to conduct a bias current therethrough;

a second transistor and a third transistor connected together in series, the third transistor having a drain terminal connected to a gate terminal of the second transistor, the third transistor is connected to the gate terminal of the first transistor, and wherein the second and third transistors are configured to conduct an operational current therethrough;

a first current source circuit coupled to the drain terminal of the first transistor, wherein the first current source circuit is configured to vary the bias current over a range of currents in a first manner; and

a second current source circuit coupled to the drain terminal of the third transistor, wherein the second current source circuit is configured to vary the operational current over a range of currents in a second manner that is different than the first manner.

2. The current mirror circuit of claim 1, wherein the first current source circuit comprises a plurality of programmable current branches coupled together in parallel, wherein at least some of the plurality of programmable current branches are configured to be selectively decoupled via a switch, and wherein a control word is configured to selectively activate or deactivate the switches to program the bias current, and wherein current weightings of the branches comply with a first weighting architecture.

3. The current mirror circuit of claim 2, wherein the second current source circuit comprises a plurality of programmable current branches coupled together in parallel, wherein at least some of the plurality of programmable current branches are configured to be selectively decoupled via a switch, and wherein a control word is configured to selectively activate or deactivate the switches to program the operational current, and wherein current weightings of the branches comply with a second weighting architecture, wherein the first and second weighting architectures are different.

4. The current mirror circuit of claim 1, wherein the second current source varies the operational current over the range of currents differently than the first current source varies the bias current over the range of currents such that the third transistor stays in a saturation mode of operation throughout the range of currents.

5. The current mirror circuit of claim 1, wherein the first current source circuit has a first group of weightings associated with a plurality of selectable paths, wherein the first group of weightings dictate the bias current.

6. The current mirror circuit of claim 5, wherein the second current source circuit has a second group of weightings associated with a plurality of selectable paths, wherein the second group of weightings dictate the operational current, and wherein the first and second group of weightings are different.

7. The current mirror circuit of claim 1, wherein the first current source circuit comprises a plurality of parallel-connected branches, wherein one or more of the branches is selectively coupled to the other branches via a switch, and wherein one of the branches is coupled to the other branches directly with no switch therein.

8. The current mirror of claim 7, wherein an amount of current conducted by each of the plurality of parallel-connected branches is a function of a weighting of each respective branch, and wherein a first group of weightings for the first current source circuit reflects a total of the weightings of each respective branch.

9. The current mirror circuit of claim 1, wherein the second current source circuit comprises a plurality of parallel-connected branches, wherein one or more of the branches is selectively coupled to the other branches via a switch, and wherein one of the branches is coupled to the other branches directly with no switch therein.

10. The current mirror circuit of claim 1, wherein the first current source circuit varies the bias current based on a first group of weightings which cause the bias current to increase over the range of currents at a first rate, and wherein the second current source circuit varies the bias current based on a second group of weightings which cause the operational current to increase over the range of currents at a second rate, wherein the first rate and the second rate are different.

17. The current mirror circuit of claim 10, wherein the second rate is greater than the first rate.

11. A method of optimizing a current mirror circuit for operation over a range of currents, comprising:

determining a desired operating current range;

simulating operation of the current mirror circuit over the desired operating current range;

ascertaining whether an active device in the current mirror circuit is in a saturation mode of operation over the desired operating current range in the simulated operation; and

altering a weighting of a first current source circuit or a second current source circuit, or both, that reside in the current mirror circuit if the active device is not in the saturation mode of operation over the desired operating current range.

12. The method of claim 11, wherein the first current source is configured to vary a bias current of the current mirror circuit over a range of currents, and wherein altering the weighting of the first current source comprises varying a rate at which the bias current is varied over the range of currents.

13. The method of claim 11, wherein the second current source is configured to vary an operational current of the current mirror circuit over a range of currents, and wherein altering the weighting of the second current source comprises varying a rate at which the operational current is varied over the range of currents.

14. The method of claim 11, wherein the current mirror comprises an input portion configured to conduct a bias current, an output portion configured to conduct an operational current, the first current source configured to generate the bias current and the second current source configured to generate the operational current.

15. The method of claim 14, wherein the first current source circuit comprises a plurality of parallel weighted, selectively activatable current paths, wherein adjusting a number of the weighted current paths that are activated alters the weighting of the first current source, and thus a rate at which the bias current is varied over the range of currents.

16. The method of claim 14, wherein the second current source circuit comprises a plurality of parallel weighted, selectively activatable current paths, wherein adjusting a number of the weighted current paths that are activated alters the weighting of the second current source, and thus a rate at which the operational current is varied over the range of currents.

18. The method of claim 11, wherein the first or second current source circuit, or both, comprise a plurality of parallel-connected branches, wherein one or more of the branches is selectively coupled to the other branches via a switch, and wherein one of the branches is coupled to the other branches directly with no switch therein.

19. The method of claim 11:

wherein the first current source is configured to vary a bias current of the current mirror circuit over the range of currents, and wherein altering the weighting of the first current source comprises varying a first rate at which the bias current is varied over the range of currents; and

wherein the second current source is configured to vary an operational current of the current mirror circuit over the range of currents, and wherein altering the weighting of the second current source comprises varying a second rate at which the operational current is varied over the range of currents, wherein the first and second rates are different.

20. The method of claim 14, wherein the output portion comprises:

a first pair of two series-connected transistors, the first pair of series-connected transistors having gate terminals connected together, the first pair of two series-connected transistors coupled between a supply potential terminal and the second current source circuit, wherein the operational current conducts therethrough; and

a second pair of series-connected transistors having gate terminals coupled to gate terminals of the first pair of series-connected transistors, and configured to conduct an output current therethrough that is related to the operational current.