Method, apparatus and system of parallel IC test
First Claim
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1. A method for testing a plurality of identical function microelectronic circuits on a common substrate, the method comprising:
- delivering a testing stimulation signal to a plurality of identical function devices under test (DUTs) in parallel on the common substrate through input paths on the common substrate;
comparing outputs of the DUTs using a plurality of comparators on the common substrate; and
testing input paths connected to the DUTs and output paths connected to the comparators, wherein said testing comprises;
delivering a testing stimulation signal to the input paths;
comparing an output of the DUTs with the input testing simulation signal;
if the output matches the input, determining that the input paths and the output paths pass the test; and
if the output does not match the input, determining that the input paths and the output paths fail the test.
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Abstract
A method, apparatus and system for integrated circuit testing, wherein a plural number of devices under test (DUTs) and a plural number of comparison apparatuses are placed on a common substrate. The DUTs all operate under the same input stimulation and each produce its own operation output. The outputs are compared by the comparison apparatuses to generate comparison characteristics which are used to filter-out the failed devices. This invention lowers the testing cost, shortens time to product mass-production, and lowers the miss rate of failed devices passed as good ones.
11 Citations
24 Claims
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1. A method for testing a plurality of identical function microelectronic circuits on a common substrate, the method comprising:
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delivering a testing stimulation signal to a plurality of identical function devices under test (DUTs) in parallel on the common substrate through input paths on the common substrate; comparing outputs of the DUTs using a plurality of comparators on the common substrate; and testing input paths connected to the DUTs and output paths connected to the comparators, wherein said testing comprises; delivering a testing stimulation signal to the input paths; comparing an output of the DUTs with the input testing simulation signal; if the output matches the input, determining that the input paths and the output paths pass the test; and if the output does not match the input, determining that the input paths and the output paths fail the test. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A semiconductor wafer comprising:
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a plurality of identical function dice under test (DUTs); and a plurality of comparators each placed between the dice on the wafer, wherein each comparator includes at least two inputs, one connected to an output of one DUT, and the other connected to an output of another DUT.
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8. A semiconductor wafer comprising:
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a plurality of identical function dice under test (DUTs); and a plurality of comparators each placed between the dice on the wafer, wherein the comparators are configured to compare output of a DUT with output of another DUT. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A semiconductor wafer comprising:
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a plurality of identical function dice under test (DUTs); a plurality of comparators each placed between the dice on the wafer; output paths connected to the comparators, wherein the output paths include configurable switches. - View Dependent Claims (20, 21, 22, 23, 24)
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Specification