Semiconductor device

• US 8,847,627 B2
• Filed: 05/16/2012
• Issued: 09/30/2014
• Est. Priority Date: 05/20/2011
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Ohnuki, Tatsuya
• Primary Examiner(s): Chang, Daniel D
• Application Number:
  US13/472,542
• Publication Number:
  US 20120292713A1
• Time in Patent Office: 867 Days
• Field of Search: 326/113, 326 95- 98, 326/112, 326119-122
• US Class Current: 326/113
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO

Abstract

A semiconductor device includes a first transistor, a second transistor, a first transistor group, and a second transistor group. The first transistor group includes a third transistor, a fourth transistor, and four terminals. The second transistor group includes fifth to eighth transistors and four terminals. The first transistor, the third transistor, the sixth transistor, and the eighth transistor are n-channel transistors, and the second transistor, the fourth transistor, the fifth transistor, and the seventh transistor are p-channel transistors.

Claims

1. A semiconductor device comprising:

a first transistor;

a second transistor;

a third transistor;

a circuit comprising a first input terminal and a second input terminal;

a high-potential power supply;

a low-potential power supply; and

an output terminal,

wherein one of a source and a drain of the first transistor is electrically connected to the low-potential power supply,

wherein the other of the source and the drain of the first transistor is electrically connected to the circuit,

wherein one of a source and a drain of the second transistor is electrically connected to the circuit and one of a source and a drain of the third transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to the high-potential power supply,

wherein the other of the source and the drain of the third transistor is electrically connected to the output terminal,

wherein the low-potential power supply is electrically connected to the output terminal through the first transistor and the circuit when a first data potential signal input to the first input terminal is same as a second data potential signal input to the second input terminal,

wherein the high-potential power supply is electrically connected to the output terminal through the second transistor when the first data potential signal is different from the second data potential signal, and

wherein the third transistor includes an oxide semiconductor layer including a channel formation region.

2. The semiconductor device according to claim 1,

wherein the third transistor is a transistor whose leakage current in an off state per micrometer of a channel width is lower than or equal to 1×

10<sup>−

17</sup> A.

3. A semiconductor device comprising:

a first transistor;

a second transistor;

a third transistor;

a first circuit comprising a first input terminal;

a second circuit comprising a second input terminal;

a high-potential power supply;

a low-potential power supply; and

an output terminal,

wherein one of a source and a drain of the first transistor is electrically connected to the low-potential power supply,

wherein the other of the source and the drain of the first transistor is electrically connected to the first circuit,

wherein the first circuit is electrically connected to the second circuit,

wherein one of a source and a drain of the second transistor is electrically connected to the second circuit and one of a source and a drain of the third transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to the high-potential power supply,

wherein the other of the source and the drain of the third transistor is electrically connected to the output terminal,

wherein the low-potential power supply is electrically connected to the output terminal through the first transistor and the first circuit and the second circuit

when a second parity bit provided by the first circuit for a data potential signal input to the first input terminal is same as a first parity bit of the data potential signal input to the second input terminal,

wherein the high-power supply is electrically connected to the output terminal through the second transistor when the second parity is different from the first parity bit, and

wherein the third transistor includes an oxide semiconductor layer including a channel formation region.

4. The semiconductor device according to claim 3,

wherein the third transistor is a transistor whose leakage current in an off state per micrometer of a channel width is lower than or equal to 1×

10<sup>−

17</sup> A.

5. A semiconductor device comprising:

a first transistor;

a second transistor;

a first transistor group including a third transistor, a fourth transistor, and first to fourth terminals; and

a second transistor group including fifth to eighth transistors and first to fourth terminals,

wherein one of a source and a drain of the first transistor is electrically connected to a low-potential power supply line,

wherein the first terminal of the first transistor group and the second terminal of the first transistor group are electrically connected to the other of the source and the drain of the first transistor,

wherein the third terminal of the first transistor group is electrically connected to the first terminal of the second transistor group,

wherein the fourth terminal of the first transistor group is electrically connected to the second terminal of the second transistor group,

wherein the third terminal of the second transistor group is electrically connected to one of a source and a drain of the second transistor and an output terminal,

wherein the fourth terminal of the second transistor group is electrically connected to the low-potential power supply line,

wherein the other of the source and the drain of the second transistor is electrically connected to a high-potential power supply line,

wherein in the first transistor group, one of a source and a drain of the third transistor is electrically connected to the first terminal of the first transistor group, the other of the source and the drain of the third transistor is electrically connected to the third terminal of the first transistor group, one of a source and a drain of the fourth transistor is electrically connected to the second terminal of the first transistor group, and the other of the source and the drain of the fourth transistor is electrically connected to the fourth terminal of the first transistor group,

wherein in the second transistor group, one of a source and a drain of the fifth transistor and one of a source and a drain of the sixth transistor are electrically connected to the first terminal of the second transistor group, one of a source and a drain of the seventh transistor and one of a source and a drain of the eighth transistor are electrically connected to the second terminal of the second transistor group, the other of the source and the drain of the fifth transistor and the other of the source and the drain of the eighth transistor are electrically connected to the third terminal of the second transistor group, and the other of the source and the drain of the sixth transistor and the other of the source and the drain of the seventh transistor are electrically connected to the fourth terminal of the second transistor group,

wherein a gate of the first transistor and a gate of the second transistor are electrically connected to a first input terminal to which a clock signal is input,

wherein gates of the third and fourth transistors included in the first transistor group are electrically connected to a second input terminal to which a data potential signal is input, and gates of the fifth to eighth transistors included in the second transistor group are electrically connected to a third input terminal to which a data potential signal is input,

wherein the first transistor, the third transistor, the sixth transistor, and the eighth transistor are n-channel transistors, and

wherein the second transistor, the fourth transistor, the fifth transistor, and the seventh transistor are p-channel transistors.

6. The semiconductor device according to claim 5, further comprising:

a ninth transistor between the second transistor and the output terminal,

wherein one of a source and a drain of the ninth transistor is electrically connected to the one of the source and the drain of the second transistor,

wherein the other of the source and the drain of the ninth transistor is electrically connected to the output terminal,

wherein a gate of the ninth transistor is electrically connected to the first input terminal, and

wherein the ninth transistor is a transistor whose leakage current in an off state per micrometer of a channel width is lower than or equal to 1×

10<sup>−

17</sup> A.

7. The semiconductor device according to claim 6, wherein the ninth transistor includes an oxide semiconductor layer including a channel formation region.

8. A semiconductor device comprising:

a first transistor;

a second transistor;

a first transistor group including a third transistor, a fourth transistor, and first to fourth terminals; and

second to m-th (m is a natural number of 3 or more) transistor groups each including fifth to eighth transistors and first to fourth terminals,

wherein one of a source and a drain of the first transistor is electrically connected to a low-potential power supply line,

wherein the first terminal of the first transistor group and the second terminal of the first transistor group are electrically connected to the other of the source and the drain of the first transistor,

wherein the third terminal of the first transistor group is electrically connected to the first terminal of the second transistor group,

wherein the fourth terminal of the first transistor group is electrically connected to the second terminal of the second transistor group,

wherein the first terminal of the m-th transistor group is electrically connected to the third terminal of the (m−

1)th transistor group,

wherein the second terminal of the m-th transistor group is electrically connected to the fourth terminal of the (m−

1)th transistor group,

wherein the third terminal of the m-th transistor group is electrically connected to one of a source and a drain of the second transistor and an output terminal,

wherein the fourth terminal of the m-th transistor group is electrically connected to the low-potential power supply line,

wherein the other of the source and the drain of the second transistor is electrically connected to a high-potential power supply line,

wherein in the first transistor group, one of a source and a drain of the third transistor is electrically connected to the first terminal of the first transistor group, the other of the source and the drain of the third transistor is electrically connected to the third terminal of the first transistor group, one of a source and a drain of the fourth transistor is electrically connected to the second terminal of the first transistor group, and the other of the source and the drain of the fourth transistor is electrically connected to the fourth terminal of the first transistor group,

wherein in the m-th transistor group, one of a source and a drain of the fifth transistor and one of a source and a drain of the sixth transistor are electrically connected to the first terminal of the m-th transistor group, one of a source and a drain of the seventh transistor and one of a source and a drain of the eighth transistor are electrically connected to the second terminal of the m-th transistor group, the other of the source and the drain of the fifth transistor and the other of the source and the drain of the eighth transistor are electrically connected to the third terminal of the m-th transistor group, and the other of the source and the drain of the sixth transistor and the other of the source and the drain of the seventh transistor are electrically connected to the fourth terminal of the m-th transistor group,

wherein a gate of the first transistor and a gate of the second transistor are electrically connected to a first input terminal to which a clock signal is input,

wherein gates of the third and fourth transistors included in the first transistor group are electrically connected to a second input terminal which a data potential signal is input, and gates of fifth to eighth transistors included in the second to m-th transistor groups are electrically connected to third to (m+1)-th input terminals to which data potential signals are input,

wherein the first transistor, the third transistor, and the sixth and eighth transistors included in the second to m-th transistor groups are n-channel transistors, and

wherein the second transistor, the fourth transistor, and the fifth and seventh transistors included in the second to m-th transistor groups are p-channel transistors.

9. The semiconductor device according to claim 8, further comprising:

a ninth transistor between the second transistor and the output terminal,

wherein one of a source and a drain of the ninth transistor is electrically connected to the one of the source and the drain of the second transistor,

wherein the other of the source and the drain of the ninth transistor is electrically connected to the output terminal,

wherein a gate of the ninth transistor is electrically connected to the first input terminal, and

wherein the ninth transistor is a transistor whose leakage current in an off state per micrometer of a channel width is lower than or equal to 1×

10<sup>−

17</sup> A.

10. The semiconductor device according to claim 9, wherein the ninth transistor includes an oxide semiconductor layer including a channel formation region.

11. A semiconductor device comprising:

first to fourth transistors;

a first transistor group including a fifth transistor, a sixth transistor, and first to fourth terminals; and

a second transistor group including seventh to tenth transistors and first to fourth terminals,

wherein one of a source and a drain of the first transistor is electrically connected to a low-potential power supply line,

wherein the first terminal of the first transistor group and the second terminal of the first transistor group are electrically connected to the other of the source and the drain of the first transistor,

wherein the third terminal of the first transistor group is electrically connected to the first terminal of the second transistor group,

wherein the fourth terminal of the first transistor group is electrically connected to the second terminal of the second transistor group,

wherein the third terminal of the second transistor group is electrically connected to one of a source and a drain of the second transistor,

wherein the fourth terminal of the second transistor group is electrically connected to one of a source and a drain of the third transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the third transistor, one of a source and a drain of the fourth transistor, and an output terminal,

wherein the other of the source and the drain of the fourth transistor is electrically connected to a high-potential power supply line,

wherein in the first transistor group, one of a source and a drain of the fifth transistor is electrically connected to the first terminal of the first transistor group, the other of the source and the drain of the fifth transistor is electrically connected to the third terminal of the first transistor group, one of a source and a drain of the sixth transistor is electrically connected to the second terminal of the first transistor group, and the other of the source and the drain of the sixth transistor is electrically connected to the fourth terminal of the first transistor group,

wherein in the second transistor group, one of a source and a drain of the seventh transistor and one of a source and a drain of the eighth transistor are electrically connected to the first terminal of the second transistor group, one of a source and a drain of the ninth transistor and one of a source and a drain of the tenth transistor are electrically connected to the second terminal of the second transistor group, the other of the source and the drain of the seventh transistor and the other of the source and the drain of the tenth transistor are electrically connected to the third terminal of the second transistor group, and the other of the source and the drain of the eighth transistor and the other of the source and the drain of the ninth transistor are electrically connected to the fourth terminal of the second transistor group,

wherein a gate of the first transistor and a gate of the fourth transistor are electrically connected to a first input terminal to which a clock signal is input,

wherein gates of the fifth and sixth transistors included in the first transistor group are electrically connected to a second input terminal to which a data potential signal is input, and gates of the seventh to tenth transistors included in the second transistor group are electrically connected to a third input terminal to which a data potential signal is input,

wherein gates of the second transistor and the third transistor are electrically connected to a fourth input terminal to which a parity bit of the data potential signal is input,

wherein the first transistor, the third transistor, the fifth transistor, the eighth transistor, and the tenth transistor are n-channel transistors, and

wherein the second transistor, the fourth transistor, the sixth transistor, the seventh transistor, and the ninth transistor are p-channel transistors.

12. The semiconductor device according to claim 11, further comprising:

an eleventh transistor between the second transistor and the output terminal,

wherein one of a source and a drain of the eleventh transistor is electrically connected to the other of the source and the drain of the second transistor, the other of the source and the drain of the third transistor, and the one of the source and the drain of the fourth transistor,

wherein the other of the source and the drain of the eleventh transistor is electrically connected to the output terminal,

wherein a gate of the eleventh transistor is electrically connected to the first input terminal, and

wherein the eleventh transistor is a transistor whose leakage current in an off state per micrometer of a channel width is lower than or equal to 1×

10¹⁷ A.

13. The semiconductor device according to claim 12, wherein the eleventh transistor includes an oxide semiconductor layer including a channel formation region.

14. A semiconductor device comprising:

first to fourth transistors;

a first transistor group including a fifth transistor, a sixth transistor, and first to fourth terminals; and

second to m-th (m is a natural number of 3 or more) transistor groups each including seventh to tenth transistors and first to fourth terminals,

wherein one of a source and a drain of the first transistor is electrically connected to a low-potential power supply line,

wherein the first terminal of the first transistor group and the second terminal of the first transistor group are electrically connected to the other of the source and the drain of the first transistor,

wherein the third terminal of the first transistor group is electrically connected to the first terminal of the second transistor group,

wherein the fourth terminal of the first transistor group is electrically connected to the second terminal of the second transistor group,

wherein the first terminal of the m-th transistor group is electrically connected to the third terminal of the (m−

1)th transistor group,

wherein the second terminal of the m-th transistor group is electrically connected to the fourth terminal of the (m−

1)th transistor group,

wherein the third terminal of the m-th transistor group is electrically connected to one of a source and a drain of the second transistor,

wherein the fourth terminal of the m-th transistor group is electrically connected to one of a source and a drain of the third transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the third transistor, one of a source and a drain of the fourth transistor, and an output terminal,

wherein the other of the source and the drain of the fourth transistor is electrically connected to a high-potential power supply line,

wherein in the first transistor group, one of a source and a drain of the fifth transistor is electrically connected to the first terminal of the first transistor group, the other of the source and the drain of the fifth transistor is electrically connected to the third terminal of the first transistor group, one of a source and a drain of the sixth transistor is electrically connected to the second terminal of the first transistor group, and the other of the source and the drain of the sixth transistor is electrically connected to the fourth terminal of the first transistor group,

wherein in the m-th transistor group, one of a source and a drain of the seventh transistor and one of a source and a drain of the eighth transistor are electrically connected to the first terminal of the m-th transistor group, one of a source and a drain of the ninth transistor and one of a source and a drain of the tenth transistor are electrically connected to the second terminal of the m-th transistor group, the other of the source and the drain of the seventh transistor and the other of the source and the drain of the tenth transistor are electrically connected to the third terminal of the m-th transistor group, and the other of the source and the drain of the eighth transistor and the other of the source and the drain of the ninth transistor are electrically connected to the fourth terminal of the m-th transistor group,

wherein a gate of the first transistor and a gate of the fourth transistor are electrically connected to a first input terminal to which a clock signal is input,

wherein gates of the fifth and sixth transistors included in the first transistor group are electrically connected to a second input terminal which a data potential signal is input, and gates of seventh to tenth transistors included in the second to m-th transistor groups are electrically connected to third to (m+1)-th input terminals to which data potential signals are input,

wherein gates of the second transistor and the third transistor are electrically connected to a (m+2)-th input terminal to which a parity bit of the data potential signal is input,

wherein the first transistor, the third transistor, the fifth transistor, and the eighth and tenth transistors included in the second to m-th transistor groups are n-channel transistors, and

wherein the second transistor, the fourth transistor, the sixth transistor, and the seventh and ninth transistors are p-channel transistors.

15. The semiconductor device according to claim 14, further comprising:

an eleventh transistor between the second transistor and the output terminal,

wherein one of a source and a drain of the eleventh transistor is electrically connected to the other of the source and the drain of the second transistor, the other of the source and the drain of the third transistor, and the one of the source and the drain of the fourth transistor,

wherein the other of the source and the drain of the eleventh transistor is electrically connected to the output terminal,

wherein a gate of the eleventh transistor is electrically connected to the first input terminal, and

wherein the eleventh transistor is a transistor whose leakage current in an off state per micrometer of a channel width is lower than or equal to 1×

10<sup>−

17</sup> A.

16. The semiconductor device according to claim 15, wherein the eleventh transistor includes an oxide semiconductor layer including a channel formation region.