Stacked amplifier with diode-based biasing

• US 8,847,689 B2
• Filed: 02/24/2010
• Issued: 09/30/2014
• Est. Priority Date: 08/19/2009
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Zhao, Yu, Pletcher, Nathan M.
• Primary Examiner(s): Pascal, Robert
• Assistant Examiner(s): NGUYEN, KHIEM D
• Application Number:
  US12/711,858
• Publication Number:
  US 20110043284A1
• Time in Patent Office: 1,679 Days
• Field of Search: 330/277, 330/311
• US Class Current: 330/311
• CPC Class Codes: H03F 1/0283 Reducing the number of DC-current paths
• CPC Class Codes: H03F 1/301 in MOSFET amplifiers H03F1/303, H03F1/305, H03F1/308 take precedence
• CPC Class Codes: H03F 3/189 High-frequency amplifiers, e.g. radio frequency amplifiers

Abstract

Techniques for improving linearity of amplifiers are described. In an exemplary design, an amplifier (e.g., a power amplifier) may include a plurality of transistors coupled in a stack and at least one diode. The plurality of transistors may receive and amplify an input signal and provide an output signal. The at least one diode may be operatively coupled to at least one transistor in the stack. Each diode may provide a variable bias voltage to an associated transistor in the stack. Each diode may have a lower voltage drop across the diode at high input power and may provide a higher bias voltage to the associated transistor at high input power. The at least one transistor may have higher gain at high input power due to the higher bias voltage from the at least one diode. The higher gain may improve the linearity of the amplifier.

Claims

1. An apparatus comprising:

an amplifier comprising a plurality of transistors coupled in a stack and to receive and amplify an input signal and provide an output signal, and at least one diode having a variable voltage drop operatively coupled in series to a gate of at least one transistor in the stack, each diode provides a variable bias voltage to an associated transistor in the stack and each of the plurality of transistors further biased by a common bias circuit.

2. The apparatus of claim 1, the at least one diode comprises a single diode operatively coupled to a single transistor in the stack, the single transistor receives the input signal and provides signal gain for the input signal.

3. The apparatus of claim 1, the at least one diode comprises one diode for each transistor in the stack, each diode operatively coupled to an associated transistor in the stack.

4. The apparatus of claim 1, each diode has a lower voltage drop across the diode at high input power and provides a higher bias voltage to the associated transistor at high input power.

5. The apparatus of claim 4, the at least one transistor has higher gain at high input power due to higher bias voltage from the at least one diode.

6. The apparatus of claim 1, the amplifier further comprising at least one resistor coupled between the at least one transistor in the stack and the at least one diode.

7. The apparatus of claim 6, each of the at least one resistor is a variable resistor.

8. The apparatus of claim 1, the amplifier further comprising a plurality of resistors coupled in a ladder and to provide a plurality of bias voltages for the plurality of transistors in the stack, the at least one diode is coupled to at least one resistor in the ladder.

9. The apparatus of claim 8, the plurality of resistors comprise at least one variable resistor to provide at least one adjustable bias voltage among the plurality of bias voltages.

10. The apparatus of claim 8, the amplifier further comprising a plurality of capacitors coupled to the plurality of resistors in the ladder, one capacitor for each transistor in the stack, each capacitor provides low impedance looking from a gate of an associated transistor in the stack.

11. The apparatus of claim 1, the plurality of transistors comprise metal oxide semiconductor (MOS) transistors.

12. The apparatus of claim 1, the plurality of transistors comprise N-channel metal oxide semiconductor (NMOS) transistors.

13. The apparatus of claim 12, the at least one diode comprises at least one NMOS transistor each coupled as a diode.

14. The apparatus of claim 1, the amplifier comprises at least three transistors coupled in the stack.

15. The apparatus of claim 1, the amplifier is a power amplifier to receive an input radio frequency (RF) signal and provide an output RF signal.

16. An integrated circuit comprising:

an amplifier comprising a plurality of metal oxide semiconductor (MOS) transistors coupled in a stack and to receive and amplify an input signal and provide an output signal, and at least one diode-connected MOS transistor having a variable voltage drop operatively coupled in series to a gate of at least one MOS transistor in the stack, each diode-connected MOS transistor provides a variable bias voltage to an associated MOS transistor in the stack and each of the plurality of MOS transistors further biased by a common bias circuit.

17. The integrated circuit of claim 16, the at least one diode-connected MOS transistor comprises a single diode-connected MOS transistor operatively coupled to a single MOS transistor in the stack, the single MOS transistor receives the input signal and provides signal gain for the input signal.

18. The integrated circuit of claim 16, the at least one diode-connected MOS transistor comprises one diode-connected MOS transistor for each MOS transistor in the stack, each diode-connected MOS transistor is operatively coupled to an associated MOS transistor in the stack.

19. The integrated circuit of claim 16, the amplifier further comprising at least one resistor coupled between the at least one diode-connected MOS transistor and the at least one MOS transistor in the stack.

20. A method of amplifying an input signal, comprising:

amplifying the input signal with a plurality of transistors coupled in a stack to obtain an output signal; and

generating at least one variable bias voltage for at least one transistor in the stack based on at least one diode having a variable voltage drop operatively coupled in series to a gate of the at least one transistor in the stack and each of the plurality of transistors further biased by a common bias circuit.

21. The method of claim 20, the generating at least one variable bias voltage comprises generating a single variable bias voltage for a single transistor in the stack based on a single diode, the single transistor receives the input signal and provides signal gain for the input signal.

22. The method of claim 20, the generating at least one variable bias voltage comprises generating a plurality of variable bias voltages for the plurality of transistors in the stack based on a plurality of diodes, one variable bias voltage for each transistor in the stack.

23. The method of claim 20, further comprising:

controlling leakage from the at least one transistor in the stack with at least one resistor coupled between the at least one transistor and the at least one diode.

24. The method of claim 20, further comprising:

generating a plurality of bias voltages for the plurality of transistors in the stack with a plurality of resistors coupled in a ladder.

25. An apparatus for amplifying an input signal, comprising:

means for amplifying the input signal to obtain an output signal, the means for amplifying comprising a plurality of transistors coupled in a stack; and

means for generating at least one variable bias voltage for at least one transistor in the stack, the means for generating comprising at least one diode having a variable voltage drop operatively coupled in series to a gate of the at least one transistor in the stack and each of the plurality of transistors further biased by a common bias circuit.