Active pixel sensor with a diagonal active area

• US 8,848,080 B2
• Filed: 10/01/2012
• Issued: 09/30/2014
• Est. Priority Date: 06/17/1999
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Round Rock Research LLC
• Inventors: Rhodes, Howard E.
• Primary Examiner(s): Berardesca, Paul
• Application Number:
  US13/632,562
• Publication Number:
  US 20130026547A1
• Time in Patent Office: 729 Days
• Field of Search: 348/294, 348/302, 348/308, 250/208.1, 257/291, 257/292
• US Class Current: 348/308
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14641 Electronic components shared by two or more pixel-elements, e.g. one amplifier shared by two pixel elements
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H04N 25/74 Circuitry for scanning or addressing the pixel array
• CPC Class Codes: H04N 25/779 Circuitry for scanning or addressing the pixel array
• CPC Class Codes: H04N 25/7795 Circuitry for generating timing or clock signals
• CPC Class Codes: H04N 3/1512 for MOS image-sensors, e.g. MOS-CCD H04N3/1581 takes precedence

Abstract

An imaging device formed as a CMOS semiconductor integrated circuit having two adjacent pixels in a row connected to a common column line and a processor based system with such an imaging device. By having adjacent pixels of a row share column lines, the CMOS imager circuit eliminates half the column lines of a traditional imager allowing the fabrication of a smaller imager. The imaging device also may be fabricated to have a diagonal active area to facilitate contact of two adjacent pixels with the single column line and allow linear row select lines, reset lines and column lines.

Claims

1. An image sensing device, comprising:

a pair of pixels, each pixel of the pair comprising a respective associated active sensor area, wherein the pair of pixels share an active area between their respective associated active sensor areas, the shared active area extending in a substantially diagonal direction with respect to addressable rows and columns of an array of pixels including the pair of pixels,

wherein the shared active area provides a connection for the respective associated active sensor areas to a common output contact.

2. The image sensing device of claim 1, wherein the common output contact provides an electrical connection for the respective associated active sensor areas to a shared column line.

3. A processor based system, comprising:

a central processing unit in communication with a system bus;

an image sensing device in communication with the system bus, the image sensing device comprising;

an array of pixels, each of the pixels comprising a respective associated active sensor area, wherein the array is arranged in rows and columns of the pixels;

wherein the pixels are arranged in the columns and rows such that adjacent pixels share an active area between their respective associated active sensor areas, each shared active area providing a connection for the respective associated active sensor areas to a common output contact; and

wherein at least one of the adjacent pixels further comprises a reset transistor, said reset transistor comprising a gate, a first source/drain region, and a second source/drain region in a linear arrangement as viewed from above the array of pixels, wherein the shared active area between the adjacent pixels extends in a substantially diagonal direction relative to the linear arrangement of the reset transistor as the array of pixels is viewed from above; and

at least one peripheral device in communication with the system bus.

4. The processor based system of claim 3, wherein sets of no more than two pixels can be considered adjacent pixels so as to share an active area.

5. The processor based system of claim 3, wherein the common output contact connects the adjacent pixels to a shared column line.

6. A computer system, comprising:

a central processing unit in communication with a system bus;

an image sensing device in communication with the system bus, the image sensing device comprising;

at least one pair of pixels, each pixel of the pair comprising a respective associated active sensor area, wherein the pair of pixels share an active area between their respective associated active sensor areas, the shared active area being shared by the pair of pixels and no other pixels, wherein at least one of the pixels of the pair of pixels further comprises a reset transistor, said reset transistor comprising a gate, a first source/drain region, and a second source/drain region in a linear arrangement as viewed from above the pixels, wherein the shared active area of the pair of pixels extends in a substantially diagonal direction relative to the linear arrangement of the reset transistor as the pair of pixels is viewed from above; and

at least one peripheral device in communication with the system bus.

7. The computer system of claim 6, wherein the shared active area provides a connection for the respective associated active sensor areas to a common output contact.

8. The computer system of claim 7, wherein the common output contact provides an electrical connection for the respective associated active sensor areas to a shared column line.