Memory device and method for driving memory device

• US 8,848,449 B2
• Filed: 05/16/2012
• Issued: 09/30/2014
• Est. Priority Date: 05/20/2011
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Endo, Masami
• Primary Examiner(s): Luu, Pho M
• Application Number:
  US13/472,549
• Publication Number:
  US 20120294080A1
• Time in Patent Office: 867 Days
• Field of Search: 365/185.2, 365/189.11, 365/182, 365/191
• US Class Current: 365/185.2
• CPC Class Codes: G11C 11/4085 Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
• CPC Class Codes: G11C 2029/1206 Location of test circuitry on chip or wafer
• CPC Class Codes: G11C 29/12005 comprising voltage or current generators
• CPC Class Codes: G11C 29/26 Accessing multiple arrays G11C29/24 takes precedence
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A memory device capable of being operated with a single potential uses capacitive coupling of a capacitor connected to a gate of a transistor for data writing. That is, the capacitive coupling is induced by inputting a signal, which is supplied by a delay circuit configured to delay a write signal having a potential equal to the power supply potential, to the capacitor. Increase in the potential of the gate by the capacitive coupling allows the transistor to be turned on in association with the power supply potential applied to the gate from a power supply. Data is written by inputting a signal having a potential equal to the power supply potential or a grounded potential to a node through the transistor.

Claims

1. A semiconductor device comprising:

a transistor comprising a gate, a first terminal, and a second terminal;

a power supply for supplying a power supply potential;

a bootstrap circuit for inputting the power supply potential to the gate, the bootstrap circuit comprising a delay circuit and a capacitor;

a first line for inputting a first signal to control the bootstrap circuit; and

a second line for inputting a second signal to the first terminal,

wherein the first signal has a potential equal to the power supply potential,

wherein the delay circuit is configured to delay the first signal and input the delayed first signal to the capacitor, and

wherein the second signal has a potential equal to the power supply potential or a grounded potential.

2. The semiconductor device according to claim 1, wherein the bootstrap circuit is configured to increase a potential of the gate by capacitive coupling of the capacitor caused by the delayed first signal when the power supply potential is input to the gate.

3. The semiconductor device according to claim 1, further comprising:

a reading circuit for reading data stored in a node to which the second terminal is connected, and

a third line for inputting a third signal to control the reading circuit,

wherein the third signal has a potential equal to the power supply potential.

4. The semiconductor device according to claim 1, wherein the transistor has a channel formation region comprising an oxide semiconductor.

5. The semiconductor device according to claim 4, wherein the oxide semiconductor comprises indium.

6. The semiconductor device according to claim 1, wherein the semiconductor device is a memory device.

7. A semiconductor device comprising:

a power supply for supplying a power supply potential;

a controller electrically connected to the power supply;

a transistor comprising a gate, a first terminal, and a second terminal, the gate being electrically connected to the controller;

a first line electrically connected to the controller;

a delay circuit electrically connected to the first line;

a first capacitor electrically connected between the delay circuit and the gate; and

a second line electrically connected to the first terminal.

8. The semiconductor device according to claim 7, wherein the controller is configured to input the power supply potential to the gate.

9. The semiconductor device according to claim 7,

wherein the first line is configured to input a first signal to the controller and the delay circuit, and

wherein the first signal has a potential equal to the power supply potential.

10. The semiconductor device according to claim 7,

wherein the second line is configured to input a second signal to the first terminal, and

wherein the second signal has a potential equal to the power supply potential.

11. The semiconductor device according to claim 7, further comprising:

a reading circuit electrically connected to the second terminal; and

a third line electrically connected to the reading circuit and configured to input a third signal to the reading circuit,

wherein the third signal has a potential equal to the power supply potential.

12. The semiconductor device according to claim 11, further comprising a second capacitor comprising a first electrode and a second electrode, wherein the first electrode of the second capacitor is electrically connected to the second terminal and the reading circuit.

13. The semiconductor device according to claim 12, wherein the second electrode of the second capacitor is grounded.

14. The semiconductor device according to claim 12, wherein the transistor has a channel formation region comprising an oxide semiconductor.

15. The semiconductor device according to claim 14, wherein the oxide semiconductor comprises indium.

16. The semiconductor device according to claim 7, wherein the semiconductor device is a memory device.

17. A semiconductor device comprising:

a power supply for supplying a power supply potential;

a first transistor comprising a gate, a first terminal, and a second terminal;

a controller comprising;

a diode electrically connected between the power supply and the gate of the first transistor; and

a second transistor comprising a gate, a first terminal, and a second terminal, the second terminal of the second transistor being electrically connected to the power supply through the diode;

a first capacitor electrically connected to the gate of the first transistor;

a first line electrically connected to the gate of the second transistor;

a first delay circuit electrically connected between the first line and the first capacitor; and

a second line electrically connected to the first terminal of the first transistor.

18. The semiconductor device according to claim 17, wherein the first terminal of the second transistor is grounded.

19. The semiconductor device according to claim 17, wherein the controller further comprises an inverter electrically connected between the first line and the gate of the second transistor.

20. The semiconductor device according to claim 17,

wherein the controller further comprises a third transistor having a gate, a first terminal, and a second terminal,

wherein the first terminal and the second terminal of the third transistor are electrically connected to the power supply and the diode, respectively,

wherein the gate of the third transistor is electrically connected to the gate of the second transistor, and

wherein a polarity of the second transistor is different from a polarity of the third transistor.

21. The semiconductor device according to claim 20, further comprising an inverter, wherein the inverter is electrically connected between the first line and the gate of the second transistor.

22. The semiconductor device according to claim 20, wherein the controller further comprises:

a NOR circuit electrically connected between the gate of the second transistor and the first line; and

a second delay circuit electrically connected between the NOR circuit and the first line.

23. The semiconductor device according to claim 22, wherein the NOR circuit is electrically connected to the first delay circuit.

24. The semiconductor device according to claim 17,

wherein the first line is configured to input a first signal to the controller and the first delay circuit, and

wherein the first signal has a potential equal to the power supply potential.

25. The semiconductor device according to claim 17,

wherein the second line is configured to input a second signal to the first terminal of the first transistor, and

wherein the second signal has a potential equal to the power supply potential.

26. The semiconductor device according to claim 17, further comprising:

a reading circuit electrically connected to the second terminal of the first transistor; and

a third line electrically connected to the reading circuit and configured to input a third signal to the reading circuit,

wherein the third signal has a potential equal to the power supply potential.

27. The semiconductor device according to claim 26, further comprising a second capacitor comprising a first electrode and a second electrode, wherein the first electrode of the second capacitor is electrically connected to the second terminal of the first transistor and the reading circuit.

28. The semiconductor device according to claim 27, wherein the second electrode of the second capacitor is grounded.

29. The semiconductor device according to claim 17, wherein the first transistor has a channel formation region comprising an oxide semiconductor.

30. The semiconductor device according to claim 29, wherein the oxide semiconductor comprises indium.

31. The semiconductor device according to claim 17, wherein the semiconductor device is a memory device.