Method and apparatus for adjusting maximum verify time in nonvolatile memory device

• US 8,848,450 B2
• Filed: 10/26/2011
• Issued: 09/30/2014
• Est. Priority Date: 11/15/2010
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kang, Dong Ku, Kim, Seung-Bum
• Primary Examiner(s): Nguyen, Tuan T
• Assistant Examiner(s): ALROBAIE, KHAMDAN N
• Application Number:
  US13/281,793
• Publication Number:
  US 20120120730A1
• Time in Patent Office: 1,070 Days
• Field of Search: 365/185.22
• US Class Current: 365/185.22
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells

Abstract

A nonvolatile memory device is programmed by decoding a received address, determining whether the received address is a first type of page address or a second type of page address, adjusting a maximum verify time of a program loop used to verify a program state of page data according to the determined type of page address, and performing a verify operation during the adjusted maximum verify time.

Claims

1. A method of operating a nonvolatile memory device, comprising:

decoding a received address and determining whether the received address is a first type of page address or a second type of page address;

adjusting a number of program verify operations per program loop used to verify a program state of page data according to the determined type of page address; and

performing a verify operation using the adjusted number of program verify operations per program loop.

2. The method of claim 1, wherein adjusting the number of program verify operations per program loop comprises:

adjusting a maximum verify time per program loop to a first time where the received address is the first type of page address; and

adjusting the maximum verify time per program loop to a second time which is longer than the first time where the received address is the second type of page address.

3. The method of claim 2, wherein a frequency of the verify operation performed during the first time is less than a frequency of the verify operation performed during the second time.

4. The method of claim 1, wherein the first type of page address is an N^th order page address, where N is a natural number, and the second page address is a (N+1)^th order page address.

5. The method of claim 4, wherein the N^th order page address is a least significant bit (LSB) page address and the (N+1)^th order page address is a most significant bit (MSB) page address.

6. The method of claim 4, wherein the N^th order page address is a least significant bit (LSB) page address or a center significant bit (CSB) page address and the (N+1)^th order page address is a most significant bit (MSB) page address.

7. The method of claim 1, wherein performing the verify operation comprises supplying a verify voltage to a selected word line to determine the program state of the page data during the adjusted number of program verify operations.

8. The method of claim 1, wherein the number of program verify operations is adjusted as a consequence of determining that a frequency adjusting function of a verify operation is selected as an option.

9. The method of claim 1, wherein the nonvolatile memory device is a NAND flash memory device.

10. A nonvolatile memory device, comprising:

a memory cell array comprising a plurality of nonvolatile memory cells connected to a plurality of word lines;

control logic configured to decode a received address, determine whether the received address is a first type of page address or a second type of page address, adjust a number of program verify operations used to verify a program state of selected memory cells in each program loop of a program operation according to the determined type of page address, and output a control code corresponding to the adjustment; and

a voltage supply circuit configured to supply a verify voltage to a selected word line connected to the selected memory cells according to the control code.

11. The memory device of claim 10, wherein the control logic adjusts the number of program verify operations to a first value where the received address is the first type of page address and adjusts the number of program verify operations to a second value greater than the first value where the received address is the second type of page address.

12. The memory device of claim 11, wherein the voltage supply circuit adjusts a level of the verify voltage several times during a second time corresponding to the number of program verify operations having the second value according to the control code where the received address is the second page address.

13. The memory device of claim 11, wherein the first type of page address is an N^th order page address, where N is a natural number, and the second type of page address is an (N+1)^th order page address.

14. The memory device of claim 10, wherein the memory cell array is one of a plurality of memory cell arrays that are three-dimensionally stacked.

15. The memory device of claim 10, wherein the memory cell array and control logic form part of a memory card.

16. A method of programming a nonvolatile memory device, comprising:

selecting a page of memory cells; and

performing a program operation on the selected page of memory cells, wherein the program operation comprises a plurality of program loops each comprising a program-execution operation and at least one program-verify operation, and wherein a number of program verify operations per program loop is determined by whether the selected page is a first type of page or a second type of page,

wherein the first type of page is a least significant bit (LSB) page or a central significant bit (CSB) page and the second type of page is a most significant bit (MSB) page.

17. The method of claim 16, wherein the at least one program-verify operation has a first duration where the selected page is the first type of page, and a second duration twice as long as the first duration where the selected page is the second type of page.

18. The method of claim 16, further comprising:

determining whether the selected page is the first type of page or the second type of page by decoding a page address of the selected page.

19. The method of claim 16, wherein the nonvolatile memory device is a NAND flash memory device.