Nonvolatile memory device, erasing method thereof, and memory system including the same
First Claim
1. A method of erasing a nonvolatile memory device including a memory string, the memory string including a plurality of memory cells, a string selection transistor, and a ground selection transistor disposed on a substrate, the method comprising:
- applying one or more word line erase voltages to a plurality of word lines connected to the memory cells;
applying a first voltage to a ground selection line connected to the ground selection transistor;
applying a second voltage from a first time to the substrate on which the memory string is disposed while applying the first voltage to the ground selection line; and
floating the ground selection line from a second time, the second time being later than the first time.
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Abstract
Provided is an erasing method of a nonvolatile memory device. The erasing method applies a word line erase voltage to a plurality of word lines connected to the memory cells respectively, applies a specific voltage to a ground selection line connected to the ground selection transistor, applies an erase voltage to a substrate in which the memory string formed during the step applying the specific voltage to the ground selection line, and floats the ground selection line in response to a voltage change of the substrate.
100 Citations
20 Claims
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1. A method of erasing a nonvolatile memory device including a memory string, the memory string including a plurality of memory cells, a string selection transistor, and a ground selection transistor disposed on a substrate, the method comprising:
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applying one or more word line erase voltages to a plurality of word lines connected to the memory cells; applying a first voltage to a ground selection line connected to the ground selection transistor; applying a second voltage from a first time to the substrate on which the memory string is disposed while applying the first voltage to the ground selection line; and floating the ground selection line from a second time, the second time being later than the first time. - View Dependent Claims (2, 3, 4, 5, 17, 18)
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6. A nonvolatile memory device comprising:
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a memory cell array comprising a plurality of memory strings, each memory string including at least one ground selection transistor formed on a first surface of a substrate, a plurality of memory cells formed on the at least one ground selection transistor, and at least one string selection transistor formed on the plurality of memory cells; an address decoder congifured to control a plurality of word lines connected to the plurality of memory cells respectively, at least one string selection line connected to the at least one string selection transistor and at least one ground selection line connected to the at least one ground selection transistor; and a substrate bias circuit configured to apply an erase voltage to the substrate from a first time, wherein the address decoder is configured to apply a first voltage to the at least one ground selection line from the first time and float the at least one ground selection line at a second time, the second time being later than the first time. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13, 14, 15, 20)
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16. The nonvolatile memory device of clam 6, further comprising:
a reading and writing circuit connected to the plurality of memory strings through a plurality of bit lines, and configured to drive the bit lines.
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19. A nonvolatile memory device comprising:
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a memory cell array comprising a plurality of memory strings, each memory string including at least one ground selection transistor on a first surface of a substrate, a plurality of memory cells on or above the at least one ground selection transistor, at least one string selection transistor on or above the plurality of memory cells, and at least one dummy cell either on the at least one ground selection transistor and beneath the at least one string selection transistor, or on the at least one ground selection transistor or beneath the at least one string selection transistor; an address decoder configured to control a plurality of word lines connected to the plurality of memory cells, at least one string selection line connected to the at least one string selection transistor, at least one dummy word line connected to the at least one dummy cell and at least one ground selection line connected to the at least one ground selection transistor; and a substrate bias circuit configured to apply an erase voltage to the substrate from a first time, wherein the address decoder is configured to apply a first voltage to the at least one ground selection line from the first time and float the at least one ground selection line at a second time, the second time being later than the first time.
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Specification