Semiconductor device and method of driving semiconductor device

• US 8,848,464 B2
• Filed: 04/25/2012
• Issued: 09/30/2014
• Est. Priority Date: 04/29/2011
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Sekine, Yusuke, Kato, Kiyoshi
• Primary Examiner(s): DINH, SON T
• Application Number:
  US13/455,227
• Publication Number:
  US 20120275245A1
• Time in Patent Office: 888 Days
• Field of Search: 365/189.15, 365/189.05, 365/149, 365/189.16, 365/189.14
• US Class Current: 365/189.15
• CPC Class Codes: G11C 11/403 with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence

Abstract

A semiconductor device which is capable of high-speed writing with less power consumption and suitable for multi-leveled memory, and verifying operation. A memory cell included in the semiconductor device included a transistor formed using an oxide semiconductor and a transistor formed using a material other than an oxide semiconductor. A variation in threshold value of the memory cells is derived before data of a data buffer is written by using a writing circuit. Data in which the variation in threshold value is compensated with respect to the data of the data buffer is written to the memory cell.

Claims

1. A semiconductor device comprising:

a bit line;

a word line;

a memory cell comprising;

a first transistor including a channel region comprising an oxide semiconductor,

a second transistor including a channel region comprising any of silicon, germanium, silicon germanium, silicon carbide, and gallium arsenide, and

a capacitor,

wherein one of a source and a drain of the first transistor and one of a source and a drain of the second transistor are electrically connected to the bit line,

wherein the other of the source and the drain of the first transistor and a gate of the second transistor are electrically connected to one of electrodes of the capacitor, and

wherein the other of the electrodes of the capacitor is electrically connected to the word line; and

a writing circuit electrically connected to the memory cell through the bit line, the writing circuit configured to input one of a plurality of write data potentials or a reference potential as a write data potential to the memory cell, and

wherein the writing circuit is configured to write the one of the plurality of write data potentials to the memory cell when a potential applied to the gate of the second transistor is higher than a threshold voltage of the second transistor.

2. The semiconductor device according to claim 1, further comprising:

a control signal generating circuit configured to output a control signal having a constant cycle;

a switching element electrically connected to the control signal generating circuit, the switching element configured to control an output of the control signal;

a potential generating circuit configured to generate the reference potential and the plurality of write data potentials each having different potential;

a data buffer electrically connected to the writing circuit and configured to hold a data to be written to the memory cell; and

a reading circuit electrically connected to the writing circuit and the memory cell, the reading circuit configured to read the write data potential of the memory cell.

3. The semiconductor device according to claim 1, further comprising a signal line electrically connected to the writing circuit,

wherein the writing circuit comprises:

a third transistor;

a fourth transistor; and

a shift register electrically connected to a gate of the third transistor;

wherein a gate of the fourth transistor is electrically connected to the signal line,

wherein the one of the plurality of write data potentials is input to one of a source and a drain of the third transistor, and

wherein the reference potential is input to one of a source and a drain of the fourth transistor.

4. The semiconductor device according to claim 3, wherein the other of the source and the drain of the third transistor is electrically connected to the other of the source and the drain of the fourth transistor.

5. The semiconductor device according to claim 1, further comprising a plurality of memory cells each electrically connected to a word line and the bit line,

wherein the memory cell and the plurality of memory cells have a variation in a threshold voltage.

6. The semiconductor device according to claim 1, wherein the channel region of the second transistor is provided in a substrate containing a semiconductor material.

7. The semiconductor device according to claim 1, wherein the oxide semiconductor contains at least one element selected from In, Ga, Sn, and Zn.

8. A semiconductor device comprising:

a bit line;

a word line;

a memory cell configured to output a first potential or a second potential, the memory cell comprising;

a first transistor electrically connected to the bit line, the first transistor including a channel region comprising an oxide semiconductor;

a second transistor electrically connected to the bit line, the second transistor including a channel region comprising any of silicon, germanium, silicon germanium, silicon carbide, and gallium arsenide; and

a capacitor electrically connected to the word line, the first transistor, and the second transistor;

a data buffer configured to hold a data to be written to the memory cell;

a potential generating circuit configured to generate a reference potential and a plurality of write data potentials;

a control signal generating circuit configured to output a control signal having a constant cycle;

a writing circuit configured to write the reference potential and one of the plurality of write data potentials as a write data potential to the memory cell;

a reading circuit configured to read the write data potential of the memory cell; and

a switching element configured to control an output of the control signal according to an input of the first potential or the second potential,

wherein the memory cell is configured to output the first potential until a potential applied to a gate of the second transistor reaches a threshold value of the second transistor,

wherein the memory cell is configured to output the second potential once the potential applied to the gate of the second transistor reaches the threshold value, and

wherein the writing circuit configured to write one of the plurality of write data potentials to the memory cell according to an output of the second potential.

9. The semiconductor device according to claim 8,

wherein the first transistor controls an input of a potential from the bit line and an output of a potential to the bit line,

wherein the second transistor controls an output of a potential to the bit line according to a potential from the word line and outputs the first potential or the second potential according to the potential applied to the gate of the second transistor, and

wherein the capacitor adjusts the potential from the word line, which is applied to the gate of the second transistor.

10. The semiconductor device according to claim 8,

wherein an electric signal of the word line changes according to the output of the control signal,

wherein the writing circuit configured to write the reference potential to the memory cell before the data is input from the data buffer, select one of the plurality of write data potentials after the data is input from the data buffer, and write, to the memory cell, the write data potential which is selected when an operation of the switching element is stopped, and

wherein the switching element configured to allow the output of the control signal to the writing circuit in a period during which the first potential is input and interrupt the output of the control signal to the writing circuit once the second potential is input.

11. The semiconductor device according to claim 10, wherein the control signal generating circuit configured to generate the control signal during the period after the reference potential is written to the memory cell and until the output of the control signal from the switching element is stopped.

12. The semiconductor device according to claim 8, wherein levels of the plurality of write data potentials are different from each other.

13. The semiconductor device according to claim 8, wherein one of a source and a drain of the first transistor is electrically connected to the gate of the second transistor.

14. The semiconductor device according to claim 13,

wherein the writing circuit is electrically connected to the other of the source and the drain of the first transistor, and

wherein the reading circuit is electrically connected to one of a source and a drain of the second transistor.

15. The semiconductor device according to claim 8, further comprising a plurality of memory cells each electrically connected to a word line and the bit line,

wherein the memory cell and the plurality of memory cells have a variation in a threshold voltage.

16. The semiconductor device according to claim 8, wherein the channel region is provided in a substrate containing a semiconductor material.

17. The semiconductor device according to claim 8, wherein the oxide semiconductor contains at least one element selected from In, Ga, Sn, and Zn.

18. A method for driving a semiconductor device comprising the steps of:

applying a reference potential generated in a potential generating circuit from a writing circuit to a gate of a second transistor in a memory cell and making a first transistor of the memory cell turn off, so that the reference potential is written to the memory cell, wherein the gate of the second transistor is electrically connected to one of a source and a drain of the first transistor and one of electrodes of a capacitor, and wherein the other of the electrodes of the capacitor is electrically connected a word line;

inputting a data stored in a data buffer to the writing circuit after applying the reference potential;

selecting one of a plurality of write data potentials generated in the potential generating circuit;

applying a first potential to the gate of the second transistor according to generating a control signal in a control signal generating circuit and changing a potential applied to the word line;

selecting another of the plurality of write data potentials according to inputting the control signal to the writing circuit; and

writing the another of the plurality of write data potentials to the memory cell when the first potential is higher than a threshold voltage of the second transistor,

wherein the first transistor includes a channel region comprising an oxide semiconductor, and

wherein the second transistor includes a channel region comprising any of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, and an organic semiconductor material.

19. The method for driving a semiconductor device according to claim 18,

wherein changing the potential is performed at least once, and

wherein selecting the another of the plurality of write data potentials is performed according to changing the potential so that the number of changing the potential is the same as the number of selecting the another of the plurality of write data potentials.

20. The method for driving a semiconductor device according to claim 18, wherein the plurality of write data potentials are different from each other.

21. The method for driving a semiconductor device according to claim 18, wherein the threshold voltage of the second transistor is different from a designed threshold voltage.

22. The method for driving a semiconductor device according to claim 18,

wherein the control signal is successively output to the writing circuit through a switching element at a constant cycle, and

wherein the switching element is stopped when the first potential is higher than the threshold voltage of the second transistor.

23. The method for driving a semiconductor device according to claim 18, wherein a driver circuit including the data buffer, the writing circuit, and the control signal generating circuit.

24. The method for driving a semiconductor device according to claim 18, wherein the plurality of write data potentials includes a plurality of potentials for writing of the data.