Transform design with scaled and non-scaled interfaces

• US 8,849,884 B2
• Filed: 03/26/2007
• Issued: 09/30/2014
• Est. Priority Date: 03/29/2006
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Reznik, Yuriy, Ludwin, Albert Scott, Chung, Hyukjune, Garudadri, Harinath, Srinivasamurthy, Naveen, Sagetong, Phoom
• Primary Examiner(s): Ngo, Chuong D
• Application Number:
  US11/691,268
• Publication Number:
  US 20070233764A1
• Time in Patent Office: 2,745 Days
• Field of Search: 708/400, 708/401, 708/402
• US Class Current: 708/401
• CPC Class Codes: G06F 17/14 Fourier, Walsh or analogous domain transformations , e.g. Laplace, Hilbert, Karhunen-Loeve, transforms for correlation function computation G06F17/156; spectrum analysers G01R23/16
• CPC Class Codes: G06F 17/147 Discrete orthonormal transforms, e.g. discrete cosine transform, discrete sine transform, and variations therefrom, e.g. modified discrete cosine transform, integer transforms approximating the discrete cosine transform G06F17/145 takes precedence
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/61 in combination with predictive coding

Abstract

Techniques for efficiently performing full and scaled transforms on data received via full and scaled interfaces, respectively, are described. A full transform is a transform that implements the complete mathematical description of the transform. A full transform operates on or provides full transform coefficients. A scaled transform is a transform that operates on or provides scaled transform coefficients, which are scaled versions of the full transform coefficients. The scaled transform may have lower computational complexity whereas the full transform may be simpler to use by applications. The full and scaled transforms may be for a 2D IDCT, which may be implemented in a separable manner with 1D IDCTs. The full and scaled transforms may also be for a 2D DCT, which may be implemented in a separable manner with 1D DCTs. The 1D IDCTs and 1D DCTs may be implemented in a computationally efficient manner.

Claims

1. An apparatus comprising:

a processor configured to;

receive a block of first input values via a first interface,

perform a full two-dimensional (2D) transform on the block of first input values to obtain a block of first output values, comprising;

scaling the block of first input values to obtain a block of scaled input values,

performing a scaled one-dimensional (1D) transform on each row of the block of scaled input values to obtain an intermediate block, and

performing a scaled 1D transform on each column of the intermediate block,

receive a block of second input values, different from the block of first input values, via a second interface, and

perform a scaled transform on the block of second input values to obtain a block of second output values; and

a memory coupled to the processor.

2. The apparatus of claim 1, wherein the processor is further configured to perform output formatting on the block of first output values to form a block of first output samples, and on the block of second output values to form a block of second output samples.

3. The apparatus of claim 1, wherein the full transform is a full inverse discrete cosine transform (IDCT) and the scaled transform is a scaled IDCT.

4. The apparatus of claim 1, wherein the full transform is a full two-dimensional (2D) inverse discrete cosine transform (IDCT) and the scaled transform is a scaled 2D IDCT.

5. The apparatus of claim 4, wherein the block of first input values comprises a block of full transform coefficients.

6. The apparatus of claim 4, wherein the block of second input values comprises a block of scaled transform coefficients.

7. An apparatus comprising:

means for receiving a block of first input values via a first interface;

means for performing a full two-dimensional (2D) transform on the block of first input values to obtain a block of first output values by;

scaling the block of first input values to obtain a block of scaled input values,

performing a scaled one-dimensional (1D) transform on each row of the block of scaled input values to obtain an intermediate block, and

performing a scaled 1D transform on each column of the intermediate block;

means for receiving a block of second input values, different from the block of first input values, via a second interface; and

means for performing a scaled transform on the block of second input values to obtain a block of second output values.

8. The apparatus of claim 7, further comprising means for performing output formatting on the block of first output values to form a block of first output samples, and on the block of second output values to form a block of second output samples.

9. A non-transitory processor-readable media for storing instructions to:

receive a block of first input values via a first interface;

perform a full two-dimensional (2D) transform on the block of first input values to obtain a block of first output values by;

scaling the block of first input values to obtain a block of scaled input values,

performing a scaled one-dimensional (1D) transform on each row of the block of scaled input values to obtain an intermediate block, and

performing a scaled 1D transform on each column of the intermediate block;

receive a block of second input values, different from the block of first input values, via a second interface; and

perform a scaled transform on the block of second input values to obtain a block of second output values.