Method, system and apparatus for handling events for partitions in a socket with sub-socket partitioning

• US 8,850,081 B2
• Filed: 09/27/2013
• Issued: 09/30/2014
• Est. Priority Date: 12/20/2007
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Harikumar, Ajay, Thomas, Tessil, Simon, Biju Puther
• Primary Examiner(s): Wong, Titus
• Application Number:
  US14/039,309
• Publication Number:
  US 20140089943A1
• Time in Patent Office: 368 Days
• Field of Search: 710/18
• US Class Current: 710/18
• CPC Class Codes: G06F 12/0806 Multiuser, multiprocessor or multiprocessing cache systems
• CPC Class Codes: G06F 2209/543 Local
• CPC Class Codes: G06F 9/5077 Logical partitioning of resources; Management or configuration of virtualized resources specific details on emulation or internal functioning of virtual machines G06F9/455
• CPC Class Codes: G06F 9/542 Event management; Broadcasting; Multicasting; Notifications

Abstract

In one aspect, the issues of events that may impact one or more partitions of sub-socket partitioning in one or more sockets can be handled. Specifically, events for partitions can be handled in a socket with sub-socket partitioning, wherein the events may include reset, interrupts, errors and reliability, availability, and serviceability (RAS) management.

Claims

1. A system comprising:

a first processor socket, configured on a semiconductor die, including a plurality of cores and to support sub-socket partitioning, wherein a first partition of the first processor socket is to run a first operating system and a second partition of the first processor socket is to run a second operating system, each of the first and second partitions associated with a partition identifier, the first processor socket further including;

a distributed cache memory coupled to the plurality of cores via a first level interconnect;

a fabric interface coupled to the first level interconnect;

a home agent coupled to the first level interconnect; and

a memory controller coupled to the home agent; and

a second processor socket coupled to the first processor socket.

2. The system of claim 1, further comprising a shared resource having:

a hardware register to store a bandwidth parameter for the first partition and the second partition; and

a hardware counter, for each partition, to track a number of consumed cycles for each request from the corresponding partition that is used for access to the shared resource during a time period.

3. The system of claim 2, wherein the shared resource comprises the home agent.

4. The system of claim 3, wherein the home agent comprises a cache controller.

5. The system of claim 2, wherein the bandwidth parameter is a number of allocated cycles for each partition.

6. The system of claim 2, wherein the bandwidth parameter is utilized during the time period, wherein the time period is stored in a second hardware counter.

7. The system of claim 1, wherein the first level interconnect comprises a ring interconnect.

8. A processor comprising:

a plurality of cores;

a first level ring interconnect to couple the plurality of cores to a distributed last level cache (LLC);

a fabric interface;

a home agent coupled to a memory controller; and

a second level interconnect to interconnect the home agent and the fabric interface, wherein the processor is to support sub-socket partitioning to utilize at least a first operating system and a second operating system within a first partition and a second partition of the processor, and to receive and isolate an event to either the first partition or the second partition based at least in part on a partition identifier associated with the event.

9. The processor of claim 8, wherein the event is a reset, interrupt, error, or reliability, availability, and serviceability (RAS) condition.

10. The processor of claim 9, wherein the reset is a partition specific reset, and a system service processor (SSP) coupled to the processor is to facilitate the partition specific reset by first setting a reset enable bit of a shared resource and then assert a global system reset.

11. The processor of claim 10, wherein the first partition includes at least one core and at least one input/output resource that are quiesced before assertion of the global system reset.

12. The processor of claim 8, further comprising an interrupt logic to facilitate an interrupt, the interrupt logic including a mapping table to map a first tuple of a message signaled interrupt (MSI) identifier, an addressing mode, and an address to a second tuple of a node identifier, a partition identifier and an interrupt logic identifier.

13. A non-transitory computer readable medium having stored thereon instructions, which if performed by a computer cause the computer to perform a method comprising:

defining a plurality of partitions within a processor socket for sub-socket partitioning, the processor socket having a plurality of cores, a memory controller, a first level ring interconnect to interconnect the plurality of cores with a distributed last level cache (LLC), a fabric interface, a home agent coupled to the memory controller, and a second level interconnect to interconnect the home agent and the fabric interface;

receiving a partition specific reset of a first partition of the processor socket; and

isolating the partition specific reset to the first partition based at least in part on a partition identifier for the first partition.

14. The non-transitory computer readable medium of claim 13, wherein the partition specific reset is caused by a system service processor (SSP) coupled to the processor socket.

15. The non-transitory computer readable medium of claim 14, wherein the partition specific reset is performed by the SSP by first setting a reset enable bit of a shared resource and then asserting a global system reset, wherein the first partition includes at least one core and at least one input/output resource that are quiesced before asserting the global system reset.

16. The non-transitory computer readable medium of claim 14, wherein the partition specific reset is performed by software in the first partition by initiating a write operation into a register into an input/output controller (ICH), wherein the write operation is trapped and sent to a first unique register of the ICH for the first partition, and to cause initiation of assertion of a first platform reset wire coupled to the SSP to cause the SSP to initiate the reset for the first partition.

17. The non-transitory computer readable medium of claim 13, wherein the partition specific reset is performed by an input/output hub (IOH) activating a reset wire to the processor socket and to an input/output device.