Independent management of data and parity logical block addresses

• US 8,850,104 B2
• Filed: 03/14/2012
• Issued: 09/30/2014
• Est. Priority Date: 03/21/2011
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Meir, Avraham, Golov, Oren, Neerman, Moshe, Sommer, Naftali
• Primary Examiner(s): Bertram, Ryan
• Application Number:
  US13/419,452
• Publication Number:
  US 20120246443A1
• Time in Patent Office: 930 Days
• Field of Search: 711/103, 714/6.1, 714/6.24
• US Class Current: 711/103
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD
• CPC Class Codes: G06F 11/1096 Parity calculation or recalculation after configuration or reconfiguration of the system
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/06 Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication G06F12/08 takes precedence
• CPC Class Codes: G06F 2211/1059 Parity-single bit-RAID5, i.e. RAID 5 implementations
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays

Abstract

A data storage method includes identifying, in a set of data items associated with respective logical addresses for storage in a memory, a first subset of the logical addresses associated with the data items containing application data, and a second subset of the logical addresses associated with the data items containing parity information that has been calculated over the application data. The data items associated with the first identified subset are stored in one or more first physical memory areas of the memory, and the data items associated with the second identified subset are stored in one or more second physical memory areas of the memory, different from the first physical memory areas. A memory management task is performed independently in the first physical memory areas and in the second physical memory areas.

Claims

1. A data storage method, comprising:

in a set of data items associated with respective logical addresses for storage in a memory, identifying a first subset of the logical addresses associated with the data items containing application data, and a second subset of the logical addresses associated with the data items containing parity information that has been calculated over the application data;

storing the data items associated with the first identified subset in one or more first physical memory areas of the memory, and storing the data items associated with the second identified subset in one or more second physical memory areas of the memory, different from the first physical memory areas;

performing a memory management task independently in the first physical memory areas and in the second physical memory areas; and

accepting the set of the data items and the respective logical addresses from a host;

wherein identifying the first and second subsets comprises identifying one or more parameters of a redundant storage scheme used by the host to produce the data items containing the parity information, and identifying the first and second subsets based on the parameters.

2. The method according to claim 1, wherein performing the memory management task comprises assigning a first over-provisioning overhead to the first physical memory areas, and assigning a second over-provisioning overhead, different from the first over-provisioning overhead, to the second physical memory areas.

3. The method according to claim 1, wherein performing the memory management task comprises performing memory compaction in the first physical memory areas, and performing the memory compaction in the second physical memory areas independently of the first physical memory areas.

4. The method according to claim 1, wherein performing the memory management task comprises performing static wear leveling in the first physical memory areas, and performing the static wear leveling in the second physical memory areas independently of the first physical memory areas.

5. The method according to claim 1, wherein identifying the parameters comprises receiving the parameters from the host.

6. The method according to claim 1, wherein identifying the parameters comprises extracting the parameters from a data structure stored in the memory.

7. The method according to claim 1, wherein identifying the parameters comprises assessing a statistical distribution of the logical addresses and deducing the parameters from the assessed statistical distribution.

8. The method according to claim 7, wherein assessing the statistical distribution comprises performing multiple modulo operations of the logical addresses.

9. The method according to claim 7, wherein deducing the parameters comprises executing an acquisition process that identifies the parameters, and subsequently executing a tracking process that verifies that the statistical distribution of subsequent accepted logical addresses matches the identified parameters.

10. The method according to claim 1, and comprising, in a memory controller, accepting the application data from a host and calculating the parity information over the application data accepted from the host.

11. The method according to claim 10, and comprising, in the memory controller:

calculating first internal parity items over the data items in the first identified subset, and calculating second internal parity items over the data items in the second identified subset;

storing the first and second internal parity items respectively in third and fourth physical memory areas in the memory, such that the first, second, third and fourth physical memory areas are different from one another; and

performing the memory management task independently in the first, second, third and fourth physical memory areas.

12. A data storage apparatus, comprising:

an interface, which is configured to accept from a host at least application data for storage in a memory; and

a processor, which is configured to;

identify, in a set of data items associated with respective logical addresses for storage in the memory, a first subset of the logical addresses associated with the data items containing the application data;

identify in the set a second subset of the logical addresses associated with the data items containing parity information that has been calculated over the application data;

store the data items associated with the first identified subset in first physical memory areas of the memory;

store the data items associated with the second identified subset in second physical memory areas of the memory, different from the first physical memory areas; and

perform a memory management task independently in the first physical memory areas and in the second physical memory areas;

wherein the interface is further configured to;

accept the set of the data items and the respective logical addresses from the host; and

provide the data items and the respective logical addresses to the processor;

wherein the processor is further configured to;

identify one or more parameters of a redundant storage scheme used by the host to produce the data items containing the parity information; and

identify the first and second subsets based on the parameters.

13. The apparatus according to claim 12, wherein the processor is configured to assign a first over-provisioning overhead to the first physical memory areas, and to assign a second over-provisioning overhead, different from the first over-provisioning overhead, to the second physical memory areas.

14. The apparatus according to claim 12, wherein the processor is configured to perform compaction in the first physical memory areas, and to perform the compaction in the second physical memory areas independently of the first physical memory areas.

15. The apparatus according to claim 12, wherein the processor is configured to perform static wear leveling in the first physical memory areas, and to perform the static wear leveling in the second physical memory areas independently of the first physical memory areas.

16. The apparatus according to claim 12, wherein the processor is configured to receive the parameters via the interface from the host.

17. The apparatus according to claim 12, wherein the processor is configured to extract the parameters from a data structure stored in the memory.

18. The apparatus according to claim 12, wherein the processor is configured to assess a statistical distribution of the logical addresses, and to deduce the parameters from the assessed statistical distribution.

19. The apparatus according to claim 18, wherein the processor is configured to assess the statistical distribution by performing multiple modulo operations of the logical addresses.

20. The apparatus according to claim 18, wherein the processor is configured to execute an acquisition process that identifies the parameters, and to subsequently execute a tracking process that verifies that the statistical distribution of subsequent accepted logical addresses matches the identified parameters.

21. The apparatus according to claim 12, wherein the processor is configured to calculate the parity information over the application data accepted from the host.

22. The apparatus according to claim 21, wherein the processor is configured to calculate first internal parity items over the data items in the first identified subset, to calculate second internal parity items over the data items in the second identified subset, to store the first and second internal parity items respectively in third and fourth physical memory areas in the memory, such that the first, second, third and fourth physical memory areas are different from one another, and to perform the memory management task independently in the first, second, third and fourth physical memory areas.

23. A data storage apparatus, comprising:

a memory; and

a processor, which is configured to;

accept from a host at least application data for storage in the memory;

identify, in a set of data items associated with respective logical addresses for storage in the memory, a first subset of the logical addresses associated with the data items containing the application data;

identify in the set a second subset of the logical addresses associated with the data items containing parity information that has been calculated over the application data;

store the data items associated with the first identified subset in first physical memory areas of the memory;

store the data items associated with the second identified subset in second physical memory areas of the memory, different from the first physical memory areas;

perform a memory management task independently in the first physical memory areas and in the second physical memory areas;

identify one or more parameters of a redundant storage scheme used by the host to produce the data items containing the parity information; and

identify the first and second subsets based on the parameter.