Content addressable memory data clustering block architecture

• US 8,850,109 B2
• Filed: 12/22/2011
• Issued: 09/30/2014
• Est. Priority Date: 12/22/2011
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Inventors: Grover, David B., Stephani, Richard J., Priebe, Gordon W.
• Primary Examiner(s): Rones, Charles
• Assistant Examiner(s): DOAN, HAN V
• Application Number:
  US13/334,254
• Publication Number:
  US 20130166850A1
• Time in Patent Office: 1,013 Days
• US Class Current: 711/108
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 12/04 Addressing variable-length words or parts of words
• CPC Class Codes: G06F 12/0607 Interleaved addressing
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An apparatus having a first circuit and a second circuit. The first circuit may be configured to (i) parse a first data word into a first data portion and a second data portion and (ii) parse a first address into a first address portion and a second address portion. The second circuit generally has a plurality of memory blocks. The second circuit may be configured to store the second data portion in a particular one of the memory blocks using (i) the first data portion to determine the particular memory block and (ii) the first address portion to determine a particular one of a plurality of locations within the particular memory block. The data portion may not be stored in the memory blocks. The particular location may be determined independently of the second address portion.

Claims

1. An apparatus comprising:

a first circuit configured to parse a first data word into a first data portion in a first signal and a second data portion in a second signal and parse a first address into a first address portion and a second address portion, wherein said first address portion contains higher order bits than said second address portion; and

a second circuit comprising a plurality of memory blocks, said second circuit being configured to store said second data portion in said second signal in a particular one of said memory blocks using said first data portion in said first signal to determine said particular memory block and said first address portion to determine a particular one of a plurality of locations within said particular memory block, and generate a second address by concatenating said first address portion and said first data portion, wherein said first data portion is not stored in said apparatus and said particular location is determined independently of said second address portion.

2. The apparatus according to claim 1, wherein said first circuit and said second circuit are implemented in a content addressable memory using data clustering.

3. The apparatus according to claim 1, wherein said second circuit is further configured to store said second address portion at said second address in a memory circuit.

4. The apparatus according to claim 1, wherein said first circuit is further configured to parse a second data word into a third data portion and a fourth data portion.

5. The apparatus according to claim 4, wherein said second circuit is further configured to generate a plurality of first indicators in response to a seek of said fourth data portion in a given one of said memory blocks determined by said third data portion and generate a plurality of second indicators in response to said seek.

6. The apparatus according to claim 5, wherein said second circuit is further configured to generate a third address portion by prioritizing said first indicators.

7. The apparatus according to claim 6, wherein said second circuit is further configured to generate a third address based on said second indicators and said third address portion.

8. The apparatus according to claim 7, wherein said second circuit is further configured to read a fourth address portion from a memory circuit at said second address and generate a fourth address by concatenating said third address portion and said fourth address portion.

9. The apparatus according to claim 1, wherein said apparatus is implemented as one or more integrated circuits.

10. A method for data clustering in a plurality of memory blocks in an apparatus, comprising the steps of:

(A) parsing a first data word into a first data portion in a first signal and a second data portion in a second signal;

(B) parsing a first address into a first address portion and a second address portion, wherein said first address portion contains higher order bits than said second address portion;

(C) storing said second data portion in said second signal in a particular one of said memory blocks using said first data portion in said first signal to determine said particular memory block and said first address portion to determine a particular one of a plurality of locations within said particular memory block, wherein said first data portion is not stored in said apparatus and said particular location is determined independently of said second address portion; and

(D) generating a second address by concatenating said first address portion and said first data portion.

11. The method according to claim 10, wherein said method is implemented in a content addressable memory using data clustering.

12. The method according to claim 10, further comprising the step of:

storing said second address portion at said second address in a memory circuit.

13. The method according to claim 10, further comprising the step of:

parsing a second data word into a third data portion and a fourth data portion.

14. The method according to claim 13, further comprising the steps of:

generating a plurality of first indicators in response to seeking said fourth data portion in a given one of said memory blocks determined by said third data portion; and

generating a plurality of second indicators in response to said seeking.

15. The method according to claim 14, further comprising the step of:

generating a third address portion by prioritizing said first indicators.

16. The method according to claim 15, further comprising the step of:

generating a third address based on said second indicators and said third address portion.

17. The method according to claim 16, further comprising the steps of:

reading a fourth address portion from a memory circuit at said second address; and

generating a fourth address by concatenating said third address portion and said fourth address portion.

18. An apparatus comprising:

means for parsing a first data word into a first data portion in a first signal and a second data portion in a second signal;

means for parsing a first address into a first address portion and a second address portion, wherein said first address portion contains higher order bits than said second address portion; and

means for storing said second data portion in said second signal in a particular one of a plurality of memory blocks using said first data portion in said first signal to determine said particular memory block and said first address portion to determine a particular one of a plurality of locations within said particular memory block, wherein said first data portion is not stored in said apparatus and said particular location is determined independently of said second address portion; and

means for generating a second address by concatenating said first address portion and said first data portion.