Operating memory with specified cache address
First Claim
1. A method for operating a memory device comprising:
- loading data into a specified address of a cache of the memory device, wherein the specified address of the cache of the memory device is specified by a first program sequence received at an interface of the memory device from a host external to the memory device; and
writing data from the specified address of the cache of the memory device to a specified address of a memory array of the memory device, wherein the specified address of the memory array of the memory device is specified by a second program sequence received at the interface from the host.
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Accused Products
Abstract
Embodiments are provided for operating a memory device by issuing certain instructions to the memory device that specify a cache and/or memory array address where an operation is to occur. One such method may include loading data into a specified address of a cache of the memory device, in which the specified address of the cache of the memory device may be specified by a first program sequence received at an interface of the memory device from a host external to the memory device. The method may also include writing the data from the specified address of the cache of the memory device to a specified address of a memory array of the memory device, in which the specified address of the memory array of the memory device may be specified by a second program sequence received at the interface from the host.
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Citations
20 Claims
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1. A method for operating a memory device comprising:
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loading data into a specified address of a cache of the memory device, wherein the specified address of the cache of the memory device is specified by a first program sequence received at an interface of the memory device from a host external to the memory device; and writing data from the specified address of the cache of the memory device to a specified address of a memory array of the memory device, wherein the specified address of the memory array of the memory device is specified by a second program sequence received at the interface from the host. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method for operating a memory device comprising:
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issuing a first instruction from a host to a memory interface to load new data into a column address of a cache of the memory device without initializing data stored at nearby column addresses of the cache, wherein the first instruction specifies the column address; and issuing a second instruction from the host to the memory interface to load data stored in the cache at or near the one of the plurality of column addresses of the cache to a specified address of a memory array of the memory device, wherein the second instruction specifies the specified address of the memory array, wherein the data stored in the cache at or near the one of the plurality of column addresses of the cache comprises the new data. - View Dependent Claims (8, 9, 10)
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11. A method for operating a memory device comprising:
communicating with a memory interface from a host, wherein communicating comprises generating a first sequence to read data from a first address of a memory array of the memory device into a specified cache address of the memory device, wherein the first sequence specifies the specified cache address, and generating a second sequence to write the data from the specified cache address of the memory device to a second address of the memory array of the memory device, wherein the second sequence specifies the second address of the memory array. - View Dependent Claims (12)
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13. A method for operating a memory device comprising:
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issuing a first instruction from a host to a memory interface to read data from a first address of a memory array of the memory device and load the data into a specified cache address of the memory device, wherein the first instruction specifies the specified cache address of the memory device; issuing a second instruction from the host to the memory interface to load new data into one of a plurality of column addresses associated with the specified cache address of the memory device, wherein the second instruction specifies the one of the plurality of column addresses; and issuing a third instruction from the host to the memory interface to write data from the specified cache address of the memory device to a second address of the memory array of the memory device, wherein the third instruction specifies the second address of the memory array of the memory device. - View Dependent Claims (14, 15)
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16. A method for operating a memory device comprising:
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loading first data to a specified cache address of the memory device by issuing a first issuance of a first instruction that specifies the specified cache address to a memory interface from a host; writing the first data from the specified cache address to a first address of a memory array of the memory device by issuing a first issuance of a second instruction that specifies the first address of the memory array of the memory device to the memory interface from the host; polling a status of the cache by issuing a first issuance of a third instruction to the memory interface; if polling indicates that the cache is ready, then loading a portion of the specified cache address with second data by issuing a second issuance of the first instruction that specifies at least the portion of the specified cache address to the memory interface from the host; polling the status of the cache and the memory device by issuing a second issuance of the third instruction to the memory interface; and if polling indicates that the cache is ready and the device is ready, writing the second data from the specified cache address to a second address of the memory array of the memory device by issuing a second issuance of the second instruction that specifies the second address of the memory array of the memory device to the memory interface from the host. - View Dependent Claims (17, 18, 19, 20)
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Specification