Systems and methods for precise generation of phase variation in digital signals

• US 8,850,259 B2
• Filed: 01/07/2011
• Issued: 09/30/2014
• Est. Priority Date: 01/07/2011
• Status: Active Grant

• Current Assignee: Keysight Technologies Singapore (Holdings) Pte. Limited. (Keysight Technologies, Inc.)
• Original Assignee: ANUE Systems (Keysight Technologies, Inc.)
• Inventors: Webb, Charles A. III
• Primary Examiner(s): Abbaszadeh, Jaweed A
• Application Number:
  US12/930,490
• Publication Number:
  US 20120176174A1
• Time in Patent Office: 1,362 Days
• Field of Search: 713/500, 713/503, 713/600
• US Class Current: 713/600
• CPC Class Codes: G06F 1/025 for functions having two-valued amplitude, e.g. Walsh functions
• CPC Class Codes: G06F 1/0321 Waveform generators, i.e. devices for generating periodical functions of time, e.g. direct digital synthesizers G06F1/0314, G06F1/035 take precedence

Abstract

Systems and methods are disclosed for precise generation of phase variation in digital signals. The disclosed signal generation embodiments generate a pattern of information bits that represents a digital signal with desired phase variations and transmit this digital pattern at high speed utilizing a serializer to generate a high speed bit stream. The high speed bit stream can be used to generate one or more digital signals, such as clock signals, having desired rates and desired phase variations. In certain embodiments, the desired phase variation can be introduced into the resulting digital signal by removing and/or inserting bits in a digital pattern thereby moving logic transitions (e.g., rising edge transitions, falling edge transitions) as desired within the resulting digital signal. In addition to clock signals, the resulting digital signals generated can be control signals, data signals and/or any other desired digital signal.

Claims

1. A system for generating a digital signal having desired phase variation, comprising:

waveform generator circuitry configured to generate a digital pattern representing a digital signal having a desired phase variation with respect to a base digital signal, the waveform generator circuitry being configured to output the digital pattern as multi-bit parallel data; and

serializer circuitry having the multi-bit parallel data as an input and having a bit stream as an output, the bit stream being single-bit serial data representing the digital signal having the desired phase variation;

wherein the waveform generator is configured to modify bits within the digital pattern to achieve the desired phase variation.

2. The system of claim 1, further comprising reference clock generator circuitry having a reference clock signal as an output, the reference clock signal being coupled to the serializer circuitry and being used to determine an input rate for the multi-bit parallel data to the serializer and to determine an output bit rate for the bit stream from the serializer.

3. The system of claim 2, wherein the reference clock generator circuitry is also coupled to the waveform generator circuitry, the reference clock signal being configured to determine an output rate for the multi-bit parallel data from the waveform generator.

4. The system of claim 1, wherein the digital signal represents edges of a digital clock signal.

5. The system of claim 1, wherein the digital signal represents a pulse signal.

6. The system of claim 1, wherein the digital signal represents at least one of an arrival of network packets and a departure of network packets.

7. The system of claim 1, wherein a bit rate for the single-bit serial data output by the serializer circuitry is at least two times faster than a rate of the multi-bit parallel data input to the serializer circuitry.

8. The system of claim 7, wherein the single-bit serial data output by the serializer circuitry is at least four times faster, than a rate of the multi-bit parallel data input to the serializer circuitry.

9. The system of claim 1, wherein the waveform generator circuitry is configured to insert one or more bits within the digital pattern to produce a phase delay within the bit stream and to remove one or more bits within the digital pattern to produce a phase advance within the bit stream.

10. The system of claim 9, wherein the waveform generator circuitry comprises waveform memory circuitry configured to store bits representing the base digital signal.

11. The system of claim 10, wherein the waveform generator circuitry comprises shifter circuitry configured to receive a waveform word from the waveform memory and to shift bits within the waveform word by one or more bits to produce a shifted waveform word representing a phase change.

12. The system of claim 11, wherein the waveform generator circuitry further comprises a bit splicer configured to receive a shifted waveform word from the shifter circuitry, to insert one or more bits into the shifted waveform word to produce a phase advance within the bit stream and to remove one or more bits from the shifted waveform word to produce a phase delay within the bit stream.

13. The system of claim 1, wherein the waveform generator circuitry is configured to receive phase control signals identifying the desired phase variation.

14. The system of claim 13, wherein the phase control signals are dithered.

15. The system of claim 1, further comprising a prescaler configured to receive the bit stream from the serializer circuitry and to produce an output signal at a different rate.

16. The system of claim 1, further comprising a cleanup phase-locked-loop (PLL) coupled to the output of the serializer and configured to generate a clean output signal.

17. A system for generating a digital signal having desired phase variation, comprising:

waveform generator circuitry configured to generate a digital pattern representing a digital signal having a desired phase variation with respect to a base digital signal, the waveform generator circuitry being configured to output the digital pattern as multi-bit parallel data; and

serializer circuitry having the multi-bit parallel data as an input and having a bit stream as an output, the bit stream being single-bit serial data representing the digital signal having the desired phase variation;

wherein waveform generator circuitry is configured to receive phase control signals identifying the desired phase variation; and

wherein the phase control signals are based upon phase change instructions from a plurality of sources.

18. A method for generating a digital signal having desired phase variation, comprising:

generating a digital pattern representing a digital signal having a desired phase variation with respect to a base digital signal;

outputting the digital pattern as multi-bit parallel data; and

serializing the multi-bit parallel data to produce a bit stream of single-bit serial data representing the digital signal having the desired phase variation;

wherein the generating step comprises modifying bits within the digital pattern to achieve the desired phase variation.

19. The method of claim 18, further comprising generating a reference clock signal and using the reference clock signal to determine an output rate for the multi-bit parallel data for the outputting step and to determine an output bit rate for the bit stream for the serializing step.

20. The method of claim 18, wherein the digital signal represents edges of a digital clock signal.

21. The method of claim 18, wherein the digital signal represents a pulse signal.

22. The method of claim 18, wherein the digital signal represents at least one of an arrival of network packets and a departure of network packets.

23. The method of claim 18, wherein a bit rate for the single-bit serial data for the serializing step is at least two times faster than a rate for the multi-bit parallel data for the outputting step.

24. The method of claim 23, wherein the bit rate for the single-bit serial data for the serializing step is at least four times faster than the rate for the multi-bit parallel data for the outputting step.

25. The method of claim 18, wherein the generating step further comprises inserting one or more bits within the digital pattern to produce a phase delay within the bit stream and removing one or more bits within the digital pattern to produce a phase advance within the bit stream.

26. The method of claim 25, further comprising storing bits representing the base digital signal within waveform memory circuitry.

27. The method of claim 26, further comprising receiving a waveform word from the waveform memory circuitry and shifting bits within the waveform word by one or more bits to produce a shifted waveform word representing a phase change.

28. The method of claim 27, further comprising inserting one or more bits into the shifted waveform word to produce a phase advance within the bit stream and removing one or more bits from the shifted waveform word to produce a phase delay within the bit stream.

29. The method of claim 18, further comprising providing phase control signals identifying the desired phase variation prior to the generating step.

30. The method of claim 29, further comprising dithering the phase control signals.

31. The method of claim 18, further comprising a prescaling the bit stream to produce an output signal at a different rate.

32. The method of claim 18, further comprising utilizing a cleanup phase-locked-loop (PLL) to generate a clean output signal.

33. A method for generating a digital signal having desired phase variation, comprising:

generating a digital pattern representing a digital signal having a desired phase variation with respect to a base digital signal;

outputting the digital pattern as multi-bit parallel data; and

serializing the multi-bit parallel data to produce a bit stream of single-bit serial data representing the digital signal having the desired phase variation;

the method further comprising;

providing phase control signals identifying the desired phase variation prior to the generating step; and

utilizing phase change instructions from a plurality of sources to provide the phase control signals.