Digital signatures

• US 8,850,281 B2
• Filed: 05/12/2009
• Issued: 09/30/2014
• Est. Priority Date: 05/12/2009
• Status: Active Grant

• Current Assignee: Empire Technology Development LLC (Allied Inventors Management, LLC), Regents of the University of California (University of California)
• Original Assignee: Empire Technology Development LLC (Allied Inventors Management, LLC)
• Inventors: Potkonjak, Miodrag
• Primary Examiner(s): Zele, Krista
• Assistant Examiner(s): DESAI, MARGISHI V
• Application Number:
  US12/464,384
• Publication Number:
  US 20100293384A1
• Time in Patent Office: 1,967 Days
• Field of Search: 713/200, 714/733
• US Class Current: 714/733
• CPC Class Codes: H04L 2209/12 Details relating to cryptographic hardware or logic circuitry
• CPC Class Codes: H04L 2209/56 Financial cryptography, e.g. electronic payment or e-cash
• CPC Class Codes: H04L 2209/805 Lightweight hardware, e.g. radio-frequency identification [RFID] or sensor
• CPC Class Codes: H04L 9/3247 involving digital signatures
• CPC Class Codes: H04L 9/3278 using physically unclonable functions [PUF]

Abstract

Technologies are generally described for secure digital signatures that employ hardware public physically unclonable functions. Each unique digital signature generator can be implemented as hardware such that manufacturing variations provide measurable performance differences resulting in unique, unclonable devices or systems. For example, slight timing variations through a large number of logic gates may be used as a hardware public physically unclonable function of the digital signature unit. The hardware digital signature unit can be parameterized such that its physical characteristics may be publicly distributed to signature verifiers. The verifiers may then simulate randomly selected portions of the signature for verification.

Claims

1. A digital signature generation device comprising:

a hardware public physically unclonable circuit comprising a plurality of interconnected components, each of the components having an inherent characteristic, not all of the components having an identical value for the inherent characteristic, the inherent characteristics causing transitory states at outputs of at least some of the components during a transition period, the transition period being between a time that an input to the hardware public physically unclonable circuit is changed and a time that all outputs of the hardware public physically unclonable circuit have reached a final value in response to the input being changed, the interconnection of the components and the inherent characteristics providing the hardware public physically unclonable circuit with unique operational characteristics capable of being parameterized;

an input register for loading input signals into the hardware public physically unclonable function; and

two or more output registers respectively connected to outputs of selected components within the hardware public physically unclonable circuit for sampling the outputs of the selected components for at least one predetermined time during the transition period to provide a digital signature value, wherein the sampled outputs result in differing digital signature values depending on when the output values of the selected components are sampled by the output registers.

2. The digital signature generation device of claim 1, further comprising a timing mechanism for determining the at least one predetermined time for sampling the output values.

3. The digital signature generation device of claim 1, further comprising an interface to a host computer, wherein the interface is coupled to the input register and the two or more output registers.

4. The digital signature generation device of claim 1, wherein the hardware public physically unclonable circuit operates with a time less than a time used for simulating the hardware public physically unclonable circuit from the parameterized characteristics.

5. The digital signature generation device of claim 1, wherein at least some of the components are logic gates.

6. The digital signature generation device of claim 1, wherein at least some of the components are nanowires.

7. The digital signature generation device of claim 1, wherein at least some of the components are photonic crystals.

21. The digital signature generation device of claim 1, wherein the hardware public physically unclonable circuit is further configured to receive a digital signature generation request that specifies input values to be loaded into the input register and specifies predetermined times for latching the output values into the output registers.

8. A method for generating digital signatures using a hardware public physically unclonable circuit, the method comprising:

loading initial values associated with a message to be signed into an input register associated with the hardware public physically unclonable circuit, wherein the hardware public physically unclonable circuit comprises a plurality of interconnected components, each of the components having an inherent characteristic, not all of the components having an identical value for the inherent characteristic, the inherent characteristics causing transitory states at outputs of at least some of the components during a transition period, the transition period being between a time that an input to the hardware public physically unclonable circuit is changed and a time that all outputs of the hardware public physically unclonable circuit have reached a final value in response to the input being changed, and a latch timing mechanism to sample the outputs of the selected components to provide digital signature values;

coupling logic signals corresponding to the initial values from the input register into the hardware public physically unclonable circuit;

propagating the logic signals through the hardware public physically unclonable circuit so as to transform the logic signals into digital signature values; and

sampling the digital signature values from the hardware public physically unclonable circuit for at least one predetermined time during the transition period into two or more output registers using the latch timing mechanism, wherein the initial values result in a first subset of the digital signature values when the output registers are latched at a first predetermined time using the latch timing mechanism, and wherein the initial values result in a second subset of the digital signature values when the output registers are latched at a second predetermined time using the latch timing mechanism.

9. The method of claim 8, further comprising initializing the input register to a known state prior to loading the initial values.

10. The method of claim 8, wherein the hardware public physically unclonable circuit generates a result with a time less than a time used for simulating the hardware public physically unclonable function to generate the result.

11. The method of claim 8, wherein the hardware public physically unclonable circuit comprises a plurality of logic gates.

12. The method of claim 8, wherein the hardware public physically unclonable circuit comprises nanowires.

13. The method of claim 8, wherein the initial values are generated by hashing the message to be signed.

14. The method of claim 8, further comprising receiving a digital signature request comprising a message to be signed and a timing specification for latching the transformed logic signals into the two or more output registers.

15. A non-transitory computer storage medium having computer-executable instructions stored thereon which, when executed by a computer system, cause the computer system to:

receive information characterizing unique parameters associated with a hardware public physically unclonable circuit and an output latch register, wherein the hardware public physically unclonable circuit comprises a plurality of interconnected components, each of the components having an inherent characteristic, not all of the components having an identical value for the inherent characteristic, the inherent characteristics causing transitory states at outputs of at least some of the components during a transition period, the transition period being between a time that an input to the hardware public physically unclonable circuit is changed and a time that all outputs of the hardware public physically unclonable circuit have reached a final value in response to the input being changed, and the output latch register samples the outputs of the selected components for at least one predetermined time during the transition period to provide a digital signature value;

receive a signed document comprising a digital signature;

select portions of the digital signature to generate by simulation;

simulate the hardware public physically unclonable circuit based on the information characterizing unique parameters to generate an expected result for the selected portion of the digital signature;

classify the digital signature as valid in response to matching the expected result for the selected portion of the digital signature with the selected portion of the received digital signature; and

classify the digital signature as suspect in response to a failure to match the expected result for the selected portion of the digital signature with the selected portion of the received digital signature.

16. The computer storage medium of claim 15, wherein selecting portions of the digital signature comprises random selection.

17. The computer storage medium of claim 15, wherein the simulated digital signature is based upon initial values associated with the signed document and timing specifications for latching outputs from the hardware public physically unclonable circuit.

18. The computer storage medium of claim 15, wherein the expected result comprises a set of results generated within a tolerance window of time.

19. The computer storage medium of claim 15, wherein the selected portion of the received digital signature comprises a portion between two or more specified output registers associated with the hardware public physically unclonable circuit.

20. The computer storage medium of claim 15, wherein the hardware public physically unclonable circuit comprises a plurality of logic gates.