System using a unique marker with each software code-block

• US 8,850,410 B2
• Filed: 01/29/2010
• Issued: 09/30/2014
• Est. Priority Date: 01/29/2010
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Burugula, Ramanjaneya S., Jann, Joefon, Pattnaik, Pratap C.
• Primary Examiner(s): Tsai, Henry
• Assistant Examiner(s): Shyu, Jing-Yih
• Application Number:
  US12/696,879
• Publication Number:
  US 20110191754A1
• Time in Patent Office: 1,705 Days
• US Class Current: 717/139
• CPC Class Codes: G06F 9/00 Arrangements for program control, e.g. control units program control for peripheral devices G06F13/10
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory

Abstract

A system and method for improving software maintainability, performance, and/or security by associating a unique marker to each software code-block; the system comprising of a plurality of processors, a plurality of code-blocks, and a marker associated with each code-block. The system may also include a special hardware register (code-block marker hardware register) in each processor for identifying the markers of the code-blocks executed by the processor, without changing any of the plurality of code-blocks.

Claims

1. A system comprising:

a marker from a plurality of markers carried by a respective one of a plurality of code-blocks;

a processor configured to detect a change in the marker in an instruction stream, and configured to identify whether to notify an operating system when there is a change in the marker; and

a compiler/interpreter to determine the marker for each code-block and tag the code-block with the marker;

wherein the plurality of code-blocks comprise an instruction set to be executed on the processor;

wherein each of the plurality of code-blocks comprises at least one of a plurality of characteristics that define how the processor uses each of the plurality of code-blocks;

wherein the processor uses each of the markers to differentiate between each of the plurality of code-blocks and tracks control transfers between any of the plurality of code-blocks.

2. The system of claim 1 wherein a register is used by the processor to identify whether to notify the operating system or not when there is a change of markers in the instruction stream.

3. The system of claim 1 wherein the compiler/interpreter determines the markers to be assigned to a single program.

4. The system of claim 3 where the compiler/interpreter determines the marker to be given to each code-block based on the characteristics of that code-block.

5. The system of claim 4 wherein the characteristics include at least one of performance, security, and serviceability.

6. The system of claim 1 wherein the compiler/interpreter reassigns markers to the code-blocks based on the number of markers supported by the system'"'"'s hardware.

7. The system of claim 1 wherein each of the markers is associated with at least one of a respective object file, or each function within the respective object file, and with a respective page-frame of code.

8. The system of claim 1 wherein the operating system notifies any interested party when at least one of a thread enters or leaves one of the plurality of code-blocks with a respective marker, and there is a respective marker change in the instruction stream.

9. A method comprising:

providing a marker to each of a plurality of code-blocks; and

identifying each of the markers, via a processor, to thereby improve at least one of security, maintainability, and performance of the plurality of code-blocks executed by that processor without changing any of the plurality of code-blocks;

wherein the plurality of code-blocks comprise an instruction set to be executed on the processor;

wherein each of the plurality of code-blocks comprises at least one of a plurality of characteristics that define how the processor uses each of the plurality of code-blocks;

wherein the processor uses each of the markers to differentiate between each of the plurality of code-blocks and tracks control transfers between any of the plurality of code-blocks.

10. The method of claim 9 further comprising associating each of the markers with at least one of a respective object file, and/or each function within the respective object file, and/or a respective page-frame of code via at least one of a compiler and an interpreter.

11. The method of claim 9 further comprises determining each of the markers'"'"' value via a loader.

12. The method of claim 9 further comprising assigning at least one of a plurality of characteristics to each of the plurality of code-blocks to define what the processor does before, during, and after executing each of the plurality of code-blocks.

13. The method of claim 9 further comprising using each of the markers to differentiate between each of the plurality of code-blocks and track control transfers between any of the plurality of code-blocks.

14. The method of claim 9 further comprising notifying, via an operating system, any interested party when at least one of a thread enters or leaves one of the plurality of code-blocks with a respective marker, and there is a respective marker change in an instruction stream.

15. A computer program product to improve system software or application software, the computer program product comprising:

a non-transitory computer readable storage medium having computer readable program code embodied therewith, the computer readable program code comprising;

computer readable program code configured to provide a marker from a plurality of markers to each one of a plurality of code-blocks; and

computer readable program code configured to identifying each of the markers, via a processor, to thereby improve at least one of security, maintainability, and performance of the plurality of code-blocks executed by a processor without changing any of the plurality of code-blocks;

wherein the plurality of code-blocks comprise an instruction set to be executed on the processor;

wherein each of the plurality of code-blocks comprises at least one of a plurality of characteristics that define how the processor uses each of the plurality of code-blocks;

wherein the processor uses each of the markers to differentiate between each of the plurality of code-blocks and tracks control transfers between any of the plurality of code-blocks.

16. The computer program product of claim 15 further comprising computer readable program code configured to associate each of the markers with at least one of a respective object file, or each function within the respective object file, and/or a respective page-frame of code.

17. The computer program product of claim 15 further comprising computer readable program code configured to assign at least one of a plurality of characteristics to each of the plurality of code-blocks to define what the processor does before, during and after the execution of each of the plurality of code-blocks.

18. The computer program product of claim 15 further comprising computer readable program code configured to use each of the markers via the processor to differentiate between each of the plurality of code-blocks and track control transfers between any of the plurality of code-blocks.

19. The computer program product of claim 15 further comprising computer readable program code configured to notify, via an operating system, any interested party when a specified thread enters or leaves one of the plurality of code-blocks with a respective marker, and there is a respective marker change in an instruction stream.

20. A system comprising:

a processor;

a plurality of code-blocks, and the plurality of code-blocks including an instruction set to be executed on the processor;

a marker from a plurality of markers carried by each of the plurality of code-blocks; and

wherein the processor is configured to identify each of the markers thereby improving at least one of security, maintainability, and performance of the plurality of code-blocks executed by that processor without changing any of the plurality of code-blocks;

wherein the plurality of code-blocks comprise an instruction set to be executed on the processor;

wherein each of the plurality of code-blocks comprises at least one of a plurality of characteristics that define how the processor uses each of the plurality of code-blocks;

wherein the processor uses each of the markers to differentiate between each of the plurality of code-blocks and tracks control transfers between any of the plurality of code-blocks.

21. The system of claim 20 wherein the processor uses each of the markers to differentiate between each of the plurality of code-blocks and track control transfers between any of the plurality of code-blocks.

22. The system of claim 21 wherein the processor, upon identifying a change in the code-block marker of instructions it is executing, can notify all other processors running in a same operating system instance, so that all the processors running that operating system can take a predetermined action as a response to a change in the code-block marker in one processor.

23. The system of claim 20 wherein an operating system notifies any interested party when at least one thread enters or leaves one of the plurality of code-blocks with a respective marker, and there is a respective marker change in an instruction stream.