Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same

• US 8,852,851 B2
• Filed: 07/10/2006
• Issued: 10/07/2014
• Est. Priority Date: 07/10/2006
• Status: Active Grant

• Current Assignee: Lodestar Licensing Group LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Zhou, Baosuo, Abatchev, Mirzafer K., Niroomand, Ardavan, Morgan, Paul A., Meng, Shuang, Greeley, Joseph N., Coppa, Brian J.
• Primary Examiner(s): RAYMOND, BRITTANY L
• Application Number:
  US11/484,271
• Publication Number:
  US 20080008969A1
• Time in Patent Office: 3,011 Days
• Field of Search: 430/311, 430/313
• US Class Current: 430/311
• CPC Class Codes: H01L 21/0335 characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/0338 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/30625 With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/3088 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 23/564 Details not otherwise provided for, e.g. protection against moisture getters H01L23/26
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.

Claims

1. A method used during fabrication of a semiconductor device, the method comprising:

providing a layer to be etched, the layer to be etched having a substantially planar elevationally outermost surface;

forming a plurality of sacrificial first spacers on the outermost surface;

forming a second spacer layer over the plurality of sacrificial first spacers;

removing a portion of the second spacer layer to form a plurality of triads of spacers on the outermost surface, the triads comprising the first spacer bracketed by second spacers on the surface with each of the spacers within the triad having a different elevational thickness and the second spacers contacting the first spacer;

forming a conformal layer over the triad;

removing a portion of the conformal layer to form groups of five adjacent spacers, the individual groups comprising the triad bracketed by third spacers;

removing the second spacers; and

etching the layer to be etched using the first and third spacers as a pattern to form a plurality of substantially similar features within the layer to be etched.

2. The method of claim 1 wherein the etching forms recesses aligned substantially equidistant along the outermost surface of the layer to be etched.

3. The method of claim 1 wherein the surfaces of all of the spacers are non-planar.

4. The method of claim 1 wherein the forming the second spacer layer on the plurality of sacrificial first spacers comprises providing a spacing layer to fill between some of the first spacers but not filling between all of the first spacers.

5. The method of claim 4 wherein the spacing layer alternates between filled and unfilled between first spacers in one cross section of the device.

6. The method of claim 1 wherein each spacer within the group of five spacers has a different elevational thickness.

7. The method of claim 1 wherein the groups of five spacers are spaced apart from one another.

8. The method of claim 1 wherein individual spacers within the groups of five spacers contact one another.

9. The method of claim 1 wherein the groups of five spacers are spaced apart from one another a distance that is substantially the same as the width of the second spacers.

10. The method of claim 1 wherein upon removal of the second spacers, the remaining spacers are substantially equally spaced along the surface to be etched.