FinFET/tri-gate channel doping for multiple threshold voltage tuning

• US 8,853,025 B2
• Filed: 02/08/2013
• Issued: 10/07/2014
• Est. Priority Date: 02/08/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Zhang, Ying, Fang, Ziwei, Xu, Jeffrey Junhao
• Primary Examiner(s): AU, BAC H
• Application Number:
  US13/763,280
• Publication Number:
  US 20140227850A1
• Time in Patent Office: 606 Days
• Field of Search: 438/156, 438/157, 438/173, 438/194, 438/217, 438/268, 438/270, 438/283
• US Class Current: 438/217
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

An embodiment method of controlling threshold voltages in a fin field effect transistor (FinFET) includes forming a dummy gate over a central portion of a fin, the central portion of the fin disposed between exterior portions of the fin unprotected by the dummy gate, removing the exterior portions of the fin and replacing the exterior portions of the fin with an epitaxially-grown silicon-containing material, applying a spin-on resist over the dummy gate and the epitaxially-grown silicon-containing material and then removing the spin-on resist over the hard mask of the dummy gate, etching away the hard mask and a polysilicon of the dummy gate to expose a gate oxide of the dummy gate, the gate oxide disposed over the central portion of the fin, and implanting ions into the central portion of the fin through the gate oxide disposed over the central portion of the fin.

Claims

1. A method of controlling threshold voltages in a fin field effect transistor (FinFET), comprising:

forming a dummy gate over a central portion of a fin, the central portion of the fin disposed between exterior portions of the fin unprotected by the dummy gate;

removing the exterior portions of the fin and replacing the exterior portions of the fin with an epitaxially-grown silicon-containing material;

applying a spin-on resist over the dummy gate and the epitaxially-grown silicon-containing material and then removing the spin-on resist over a hard mask of the dummy gate;

etching away the hard mask and a polysilicon of the dummy gate to expose a gate oxide of the dummy gate, the gate oxide disposed over the central portion of the fin; and

implanting ions into the central portion of the fin through the gate oxide disposed over the central portion of the fin.

2. The method of claim 1, further comprising removing any of the spin-on resist remaining after the ions have been implanted and then performing an annealing process to re-crystallize the fin.

3. The method of claim 1, further comprising performing the ion implantation at a temperature of between about 25°

C. and about 600°

C.

4. The method of claim 1, further comprising performing an annealing process to re-crystallize the fin, the annealing process performed immediately after the ion implantation.

5. The method of claim 1, further comprising performing an annealing process to re-crystallize the fin, the annealing process performed while dummy spacers are situated along the gate oxide disposed over the central portion of the fin.

6. The method of claim 1, further comprising performing an annealing process to re-crystallize the fin, the annealing process performed after a protective layer has been formed over the gate oxide disposed over the central portion of the fin.

7. The method of claim 1, further comprising removing the spin-on resist over the hard mask of the dummy gate through chemical down-stream etching.

8. The method of claim 1, further comprising etching away the hard mask through one of dry etching, wet etching, chemical down-stream etching, chemical oxide removal, and combinations thereof.

9. The method of claim 1, further comprising etching away the polysilicon of the dummy gate through one of dry etching, wet etching, chemical down-stream etching, and combinations thereof.

10. The method of claim 1, further comprising forming a lightly doped drain in the central portion of the fin prior to the dummy gate being formed.

11. The method of claim 1, wherein the epitaxially-grown silicon-containing material is silicon germanium (SiGe).

12. The method of claim 1, wherein the epitaxially-grown silicon-containing material is one of silicon doped with carbide (SiC), silicon doped with phosphorus (SiP), and silicon doped with carbon and phosphorus (SiCP).

13. A method of controlling threshold voltages in a fin field effect transistor (FinFET), comprising:

forming a dummy gate over a central portion of a fin, the central portion of the fin disposed between exterior portions of the fin unprotected by the dummy gate;

removing the exterior portions of the fin and replacing the exterior portions of the fin with an epitaxially-grown silicon-containing material;

applying a spin-on resist over the dummy gate and the epitaxially-grown silicon-containing material and then removing the spin-on resist over a hard mask of the dummy gate;

etching away the hard mask and a portion of a polysilicon of the dummy gate to expose a gate oxide of the dummy gate and to form polysilicon spacers, the gate oxide disposed over the central portion of the fin; and

implanting ions into the central portion of the fin through the gate oxide disposed over the central portion of the fin.

14. The method of claim 13, further comprising further comprising performing the ion implantation at a temperature of between about 25°

C. and about 600°

C.

15. The method of claim 13, further comprising performing an annealing process to re-crystallize the fin, the annealing process performed immediately after the ion implantation.

16. The method of claim 13, further comprising performing an annealing process to re-crystallize the fin, the annealing process performed before the polysilicon spacers are removed.

17. A method of controlling threshold voltages in a fin field effect transistor (FinFET), comprising:

forming a dummy gate over a central portion of a fin;

replacing exterior portions of the fin unprotected by the dummy gate with an epitaxially-grown silicon-containing material;

applying a spin-on resist over the dummy gate and the epitaxially-grown silicon-containing material and then removing the spin-on resist over a hard mask of the dummy gate;

etching away the hard mask and a polysilicon of the dummy gate to expose a gate oxide of the dummy gate, the gate oxide disposed over the central portion of the fin;

implanting ions into the central portion of the fin through the gate oxide disposed over the central portion of the fin; and

performing an annealing process to re-crystallize the fin.

18. The method of claim 17, further comprising removing any of the spin-on resist remaining after the ions have been implanted and performing the ion implantation at a temperature of between about 25°

C. and about 600°

C.

19. The method of claim 17, further comprising performing the annealing process immediately after the ion implantation.

20. The method of claim 17, further comprising performing the annealing process after at least one of dummy spacers and a protective layer have been formed over the gate oxide disposed over the central portion of the fin.