Semiconductor device

• US 8,853,684 B2
• Filed: 05/17/2011
• Issued: 10/07/2014
• Est. Priority Date: 05/21/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Endo, Yuta, Sasaki, Toshinari, Noda, Kosei, Sato, Mizuho, Ichijo, Mitsuhiro, Endo, Toshiya
• Primary Examiner(s): Nguyen, Cuong Q
• Assistant Examiner(s): Gebreyesus, Yosef
• Application Number:
  US13/109,594
• Publication Number:
  US 20110284854A1
• Time in Patent Office: 1,239 Days
• Field of Search: 257/59, 257/79, 257/E29.296, 257/40, 257/43, 257/E21.412, 257/E29.273, 257/E21.212, 257/E33.053, 438/104, 438/161
• US Class Current: 257/43
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

In a transistor having a top-gate structure in which a gate electrode layer overlaps with an oxide semiconductor layer which forms a channel region with a gate insulating layer interposed therebetween, when a large amount of hydrogen is contained in the insulating layer, hydrogen is diffused into the oxide semiconductor layer because the insulating layer is in contact with the oxide semiconductor layer; thus, electric characteristics of the transistor are degraded. An object is to provide a semiconductor device having favorable electric characteristics. An insulating layer in which the concentration of hydrogen is less than 6×10²⁰ atoms/cm³ is used for the insulating layer being in contact with oxide semiconductor layer which forms the channel region. Using the insulating layer, diffusion of hydrogen can be prevented and a semiconductor device having favorable electric characteristics can be provided.

Claims

1. A semiconductor device comprising:

an insulating layer including a first region;

a source electrode layer over the insulating layer;

a drain electrode layer over the insulating layer;

an oxide semiconductor layer over the source electrode layer and the drain electrode layer, the oxide semiconductor layer including a second region and a third region; and

a gate insulating layer over the oxide semiconductor layer, the gate insulating layer including a fourth region;

wherein;

the first region is in contact with the second region;

the third region is in contact with the fourth region; and

a concentration of hydrogen in a part of the insulating layer is greater than zero and less than 6×

10²⁰ atoms/cm³.

2. The semiconductor device according to claim 1, wherein the insulating layer and the gate insulating layer are oxide insulating layers.

3. The semiconductor device according to claim 2, wherein the oxide insulating layers are silicon oxide, silicon oxynitride, silicon nitride oxide, hafnium oxide, aluminum oxide, or tantalum oxide.

4. The semiconductor device according to claim 1, further comprising a gate electrode layer over the gate insulating layer, wherein the gate electrode layer overlaps with the oxide semiconductor layer with the gate insulating layer interposed therebetween, and the gate electrode layer is provided between the source electrode layer and the drain electrode layer.

5. The semiconductor device according to claim 1, wherein a concentration of hydrogen in a part of the gate insulating layer is less than 6×

10²⁰ atoms/cm³.

6. The semiconductor device according to claim 1, wherein the concentration of hydrogen in the part of the insulating layer is less than or equal to 5×

10¹⁹ atoms/cm³.

7. The semiconductor device according to claim 6, wherein a concentration of hydrogen in a part of the gate insulating layer is less than or equal to 5×

10¹⁹ atoms/cm³.

8. A semiconductor device comprising:

an insulating layer including a first region;

an oxide semiconductor layer over the insulating layer, the oxide semiconductor layer including a second region and a third region;

a source electrode layer electrically connected to the oxide semiconductor layer;

a drain electrode layer electrically connected to the oxide semiconductor layer; and

a gate insulating layer over the source electrode layer and the drain electrode layer, the gate insulating layer including a fourth region,

wherein;

the first region is in contact with the second region;

the third region is in contact with the fourth region; and

a concentration of hydrogen in a part of the insulating layer is greater than zero and less than 6×

10²⁰ atoms/cm³.

9. The semiconductor device according to claim 8, wherein the insulating layer and the gate insulating layer are oxide insulating layers.

10. The semiconductor device according to claim 9, wherein the oxide insulating layers are silicon oxide, silicon oxynitride, silicon nitride oxide, hafnium oxide, aluminum oxide, or tantalum oxide.

11. The semiconductor device according to claim 8, further comprising a gate electrode layer over the gate insulating layer, wherein the gate electrode layer overlaps with the oxide semiconductor layer with the gate insulating layer interposed therebetween, and the gate electrode layer is provided between the source electrode layer and the drain electrode layer.

12. The semiconductor device according to claim 8, wherein a concentration of hydrogen in a part of the gate insulating layer is less than 6×

10²⁰ atoms/cm³.

13. The semiconductor device according to claim 8, wherein the concentration of hydrogen in the part of the insulating layer is less than or equal to 5×

10¹⁹ atoms/cm³.

14. The semiconductor device according to claim 13, wherein a concentration of hydrogen in a part of the gate insulating layer is less than or equal to 5×

10¹⁹ atoms/cm³.

15. A method for manufacturing a semiconductor device comprising the steps of:

forming an insulating layer by plasma CVD using SiF₄ as a deposition gas;

forming a source electrode layer and a drain electrode layer over the insulating layer;

forming an oxide semiconductor layer over the insulating layer; and

forming a gate insulating layer over the source electrode layer, the drain electrode layer and the oxide semiconductor layer,

wherein the source electrode layer is in contact with the oxide semiconductor layer,

wherein the drain electrode layer is in contact with the oxide semiconductor layer,

wherein the gate insulating layer is over the source electrode layer and the drain electrode layer, and the gate insulating layer is in contact with the oxide semiconductor layer, and

wherein a concentration of hydrogen in a part of the insulating layer is greater than zero and less than 6×

10²⁰ atoms/cm³.

16. The method for manufacturing a semiconductor device according to claim 15, wherein the insulating layer and the gate insulating layer are oxide insulating layers.

17. The method for manufacturing a semiconductor device according to claim 16, wherein the oxide insulating layers comprise at least one of silicon oxide, silicon oxynitride, silicon nitride oxide, hafnium oxide, aluminum oxide, or tantalum oxide.

18. The method for manufacturing a semiconductor device according to claim 15, further comprising the step of forming a gate electrode layer over the gate insulating layer,

wherein the gate electrode layer overlaps with the oxide semiconductor layer with the gate insulating layer interposed therebetween, and the gate electrode layer is provided between the source electrode layer and the drain electrode layer.

19. The method for manufacturing a semiconductor device according to claim 15, wherein a concentration of hydrogen in a part of the gate insulating layer is less than 6×

10²⁰ atoms/cm³.

20. The method for manufacturing a semiconductor device according to claim 15, wherein the concentration of hydrogen in the part of the insulating layer is less than or equal to 5×

10¹⁹ atoms/cm³.

21. The method for manufacturing a semiconductor device according to claim 20, wherein a concentration of hydrogen in a part of the gate insulating layer is less than or equal to 5×

10¹⁹ atoms/cm³.

22. The method for manufacturing a semiconductor device according to claim 15, wherein the insulating layer is formed by plasma CVD using an oxidizing gas of N₂O or O₂.

23. The method for manufacturing a semiconductor device according to claim 22, wherein the insulating layer is formed by plasma CVD using an argon gas.