Cross-coupling of gate conductor line and active region in semiconductor devices
First Claim
1. A semiconductor structure comprising:
- a gate dielectric contacting a portion of an active region comprising a semiconductor material and located in a substrate;
a gate conductor of unitary construction comprising a first gate conductor portion that overlies said gate dielectric and a second gate conductor portion that contacts a semiconductor surface, wherein said semiconductor surface is selected from a surface of said active region and a surface of another active region located in said substrate; and
a gate spacer laterally contacting, and surrounding, said gate conductor, wherein an edge of a bottommost surface of said gate conductor coincides with an inner periphery of a bottom surface of said gate spacer and another edge of said bottommost surface of said gate conductor coincides with an edge of a bottom surface of said gate dielectric.
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Accused Products
Abstract
Cross-coupling between a gate conductor and an active region of a semiconductor substrate is provided by forming a gate dielectric layer on the semiconductor substrate and lithographically patterning the gate dielectric layer to form opening therein over a portion of the active region at which electrical contact with the gate conductor is desired. After implanting electrical dopants, a gate conductor layer is deposited and patterned. A remaining portion of the gate conductor layer includes an integral conductor structure, which includes a first portion overlying a gate dielectric over an active region and a second portion contacting the semiconductor material of the same active region or a different active region. The gate dielectric layer can be deposited within gate cavities in planarization dielectric material layer in a replacement gate scheme, or can be deposited on planar surfaces of active regions and/or shallow trench isolation structures in a gate first processing scheme.
22 Citations
19 Claims
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1. A semiconductor structure comprising:
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a gate dielectric contacting a portion of an active region comprising a semiconductor material and located in a substrate; a gate conductor of unitary construction comprising a first gate conductor portion that overlies said gate dielectric and a second gate conductor portion that contacts a semiconductor surface, wherein said semiconductor surface is selected from a surface of said active region and a surface of another active region located in said substrate; and a gate spacer laterally contacting, and surrounding, said gate conductor, wherein an edge of a bottommost surface of said gate conductor coincides with an inner periphery of a bottom surface of said gate spacer and another edge of said bottommost surface of said gate conductor coincides with an edge of a bottom surface of said gate dielectric. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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Specification