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CMOS devices with stressed channel regions, and methods for fabricating the same

  • US 8,853,746 B2
  • Filed: 06/29/2006
  • Issued: 10/07/2014
  • Est. Priority Date: 06/29/2006
  • Status: Active Grant
First Claim
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1. A semiconductor device comprising:

  • a p-type field effect transistor (FET) having a channel region located in a semiconductor device structure, said semiconductor device structure having a top surface that is oriented along one of a first set of equivalent crystal planes and one or more additional surfaces that are oriented along a second, different set of equivalent crystal planes, said one or more additional surfaces form acute angles with the top surface of the semiconductor device structure; and

    one or more stressor layers adjacent to the channel region of the p-type FET and adjacent to said one or more additional surfaces of the semiconductor device structure, said one or more stressor layers are arranged and constructed to apply compressive stress to the channel region of the p-type FET, and have a lattice constant smaller than that of the semiconductor device structure, wherein a tensile stress is created in the stressor layers.

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