CMOS devices with stressed channel regions, and methods for fabricating the same

• US 8,853,746 B2
• Filed: 06/29/2006
• Issued: 10/07/2014
• Est. Priority Date: 06/29/2006
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Chen, Xiangdong, Dyer, Thomas W., Settlemyer, Kenneth, Yang, Haining S.
• Primary Examiner(s): Lam, Cathy N
• Application Number:
  US11/427,495
• Publication Number:
  US 20080001182A1
• Time in Patent Office: 3,022 Days
• Field of Search: 257/627, 257/628, 257/69, 257/19, 257/255, 257/288, 257/347
• US Class Current: 257/255
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/7624 using semiconductor on insulator [SOI] technology H01L21/76297 takes precedence; manufacture of integrated circuits on insulating substrates H01L21/84; silicon on sapphire [SOS] technology H01L21/86
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

The present invention relates to improved complementary metal-oxide-semiconductor (CMOS) devices with stressed channel regions. Specifically, each improved CMOS device comprises an field effect transistor (FET) having a channel region located in a semiconductor device structure, which has a top surface oriented along one of a first set of equivalent crystal planes and one or more additional surfaces oriented along a second, different set of equivalent crystal planes. Such additional surfaces can be readily formed by crystallographic etching. Further, one or more stressor layers with intrinsic compressive or tensile stress are located over the additional surfaces of the semiconductor device structure and are arranged and constructed to apply tensile or compressive stress to the channel region of the FET. Such stressor layers can be formed by pseudomorphic growth of a semiconductor material having a lattice constant different from the semiconductor device structure.

Claims

1. A semiconductor device comprising:

a p-type field effect transistor (FET) having a channel region located in a semiconductor device structure, said semiconductor device structure having a top surface that is oriented along one of a first set of equivalent crystal planes and one or more additional surfaces that are oriented along a second, different set of equivalent crystal planes, said one or more additional surfaces form acute angles with the top surface of the semiconductor device structure; and

one or more stressor layers adjacent to the channel region of the p-type FET and adjacent to said one or more additional surfaces of the semiconductor device structure, said one or more stressor layers are arranged and constructed to apply compressive stress to the channel region of the p-type FET, and have a lattice constant smaller than that of the semiconductor device structure, wherein a tensile stress is created in the stressor layers.

2. The semiconductor device of claim 1, wherein the semiconductor device structure comprises single crystal silicon, and the first and second sets of equivalent crystal planes are selected from the group consisting of the {100}, {110}, and {111} planes of silicon.

3. The semiconductor device of claim 1, wherein the semiconductor device structure is located over a substrate that comprises at least one insulator layer with a base semiconductor substrate layer thereunder, forming a semiconductor-on-insulator (SOI) structure.

4. The semiconductor device of claim 1, wherein the semiconductor device structure is located in a bulk semiconductor substrate structure.

5. The semiconductor device of claim 1, wherein the one or more stressor layers are comprised of Si:

C and the channel region located in the semiconductor device structure is composed of silicon, silicon germanium or a combination thereof.

6. The semiconductor device of claim 1, wherein the p-type field effect transistor (FET) comprises a gate dielectric comprised of SiO₂, HfO₂, ZrO₂, Al₂O₃, TiO₂, La₂O₃, SrTiO₃, LaAlO₃ or mixtures thereof.

7. The semiconductor device of claim 1, wherein the p-type field effect transistor (FET) comprises a gate conductor comprised of polysilicon.

8. The semiconductor device of claim 1, wherein the semiconductor device structure is present on an upper semiconductor layer of an SOI substrate.

9. The semiconductor device of claim 8, where the upper semiconductor layer comprises a single crystal semiconductor material selected from the group consisting of Si, SiC, SiGe, SiGeC, Ge alloys, GaAs, InAs, InP, III-V compound semiconductors, II-VI compound semiconductors and combinations thereof.

10. A semiconductor device comprising:

a p-channel field effect transistor (p-FET) having a p-doped channel region located in a semiconductor device structure, said semiconductor device structure having a top surface that is oriented along one of a first set of equivalent crystal planes and one or more additional surfaces that are oriented along a second, different set of equivalent crystal planes, wherein the one or more additional surfaces form acute angles with the top surface of the semiconductor device structure, wherein the semiconductor device structure comprises single crystal silicon, and the first and second sets of equivalent crystal planes are selected from the group consisting of the {100}, {110}, and {111} planes of silicon; and

one or more stressor layers adjacent to said one or more additional surfaces of the semiconductor device structure and adjacent to the p-doped channel region of the p-FET to apply compressive stress to the p-doped channel region of the p-FET, wherein the one or more stressor layers have a lattice constant smaller than that of the semiconductor device structure, wherein a tensile stress is created in the stressor layers.