Dense arrays and charge storage devices

• US 8,853,765 B2
• Filed: 03/27/2014
• Issued: 10/07/2014
• Est. Priority Date: 08/14/2000
• Status: Expired due to Fees

• Current Assignee: Woden Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Lee, Thomas H., Subramanian, Vivek, Cleeves, James M., Kouznetsov, Igor G., Johnson, Mark G., Farmwald, Paul Michael
• Primary Examiner(s): HA, NATHAN W
• Application Number:
  US14/227,644
• Publication Number:
  US 20140225180A1
• Time in Patent Office: 194 Days
• Field of Search: 257/314, 257/316, 257/321, 257/324
• US Class Current: 257/321
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 2211/5612 Multilevel memory cell with more than one floating gate
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/76819 Smoothing of the dielectric planarisation of insulating materials per se H01L21/31051
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0626 with a localised breakdown region, e.g. built-in avalanching region in self-protected thyristors H01L29/7424
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/1604 Amorphous materials
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/42332 with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
• CPC Class Codes: H01L 29/42364 : characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/511 : with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/513 : the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 : the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 : the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66825 : with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 : with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7391 : Gated diode structures
• CPC Class Codes: H01L 29/78642 : Vertical transistors
• CPC Class Codes: H01L 29/7881 : Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/7889 : Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H01L 29/792 : with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H01L 29/7926 : Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H01L 29/861 : Diodes
• CPC Class Codes: H01L 29/8616 : Charge trapping diodes
• CPC Class Codes: H10B 20/00 : Read-only memory [ROM] devices
• CPC Class Codes: H10B 20/60 : Peripheral circuit regions
• CPC Class Codes: H10B 41/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/27 : the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/30 : characterised by the memory core region
• CPC Class Codes: H10B 41/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/60 : the control gate being a doped region, e.g. single-poly memory cell
• CPC Class Codes: H10B 43/10 : characterised by the top-view layout
• CPC Class Codes: H10B 43/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/23 : with source and drain on different levels, e.g. with sloping channels
• CPC Class Codes: H10B 43/27 : the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/30 : characterised by the memory core region
• CPC Class Codes: H10B 43/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 69/00 : Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

Claims

1. A monolithic three-dimensional semiconductor memory device, said memory device comprising:

a plurality of horizontally separated pillar structures disposed above a silicon substrate wherein each of said pillar structures includes two or more memory elements vertically disposed relative to the silicon substrate and vertically separated from each other, each of said pillar structures comprising;

a vertical semiconductor region;

a charge storage medium comprising one or more layers, wherein said charge storage medium is laterally disposed relative to the vertical semiconductor region; and

at least one control gate laterally disposed relative to the charge storage medium wherein said pillar structures are arranged in two or more horizontal rows, each of said horizontal rows having two or more said pillar structures and

wherein said control gate is common among at least two said pillar structures in one of said horizontal rows and among at least two said pillar structures in a different one of at least two said horizontal rows; and

driver circuitry associated with the operation of one or more of said memory elements.

2. The memory device of claim 1, wherein the control gate of at least one of said pillar structures comprises a metal conductor.

3. The memory device of claim 1, wherein the charge storage medium of at least one of said pillar structures comprises an ONO stack.

4. The memory device of claim 3, wherein the charge storage medium of at least one of said pillar structures further includes an alumina layer.

5. The memory device of claim 1, wherein the charge storage medium of at least one of said pillar structures comprises a floating gate.

6. The memory device of claim 1, wherein at least one of said pillar structures has a substantially circular shape when viewed from above.

7. The memory device of claim 1, wherein the vertical semiconductor region of at least one of said pillar structures comprises a semiconductor material selected from a group consisting of a polycrystalline semiconductor material and an amorphous semiconductor material.

8. The memory device of claim 7, wherein the charge storage medium of said at least one of said pillar structures comprises an ONO stack.

9. The memory device of claim 8, wherein at least one of said pillar structures has a substantially circular shape when viewed from above and wherein the control gate of said at least one of said pillar structures comprises a metal conductor.

10. The memory device of claim 1, wherein the driver circuitry is at least partially in the silicon substrate and below the plurality of horizontally separated pillar structures.

11. The memory device of claim 1, wherein each of said pillar structures further comprises a conductor disposed between the two or more memory elements.

12. A monolithic three-dimensional semiconductor memory device, said memory device comprising:

a plurality of horizontally separated pillar structures disposed above a silicon substrate wherein each of said pillar structures includes two or more memory elements vertically disposed relative to the silicon substrate and vertically separated from each other, each of said pillar structures comprising;

a vertical semiconductor region;

a charge storage medium, wherein said charge storage medium is laterally disposed relative to said vertical semiconductor region and wherein at least a portion of the charge storage medium is common between two or more memory elements within a pillar structure; and

at least one control gate laterally disposed relative to the charge storage medium wherein said pillar structures are arranged in two or more horizontal rows, each of said horizontal rows having two or more said pillar structures, and

wherein said control gate is common among at least two said pillar structures in one of said horizontal rows and among at least two said pillar structures in a different one of at least two said horizontal rows; and

driver circuitry associated with the operation of one or more of said memory elements.

13. The memory device of claim 12, wherein the charge storage medium of at least one of said memory elements comprises nanocrystals.

14. The memory device of claim 12, wherein the charge storage medium of at least one of said pillar structures comprises an ONO stack.

15. The memory device of claim 14, wherein said charge storage medium of at least one of said pillar structures further includes an alumina layer.

16. The memory device of claim 12, wherein the vertical semiconductor region of at least one of said pillar structures comprises a semiconductor material selected from a group consisting of a polycrystalline semiconductor material and an amorphous semiconductor material.

17. The memory device of claim 16, wherein the charge storage medium of said at least one of said pillar structures comprises an ONO stack.

18. The memory device of claim 12, wherein the driver circuitry is at least partially in the silicon substrate and below the plurality of horizontally separated pillar structures.

19. The memory device of claim 12, wherein each of the pillar structures further comprises a conductor disposed between the two or more memory elements.

20. A monolithic three-dimensional semiconductor memory device, said memory device comprising:

a plurality of memory device levels vertically disposed above a silicon substrate wherein said memory device levels have a plurality of memory elements comprising a charge storage medium and a control gate horizontally disposed relative to said charge storage medium;

said memory elements in a memory device level being horizontally separated from each other and arranged in two or more horizontal rows of two or more memory elements;

at least one of said memory device levels having memory elements substantially vertically aligned with memory elements of a vertically adjacent memory device level; and

at least one control gate being common among at least two memory elements in one of said horizontal rows in one of said memory device levels and among at least two memory elements in a second one of said horizontal rows in said one of said memory device levels; and

driver circuitry associated with the operation of one or more of said memory elements.

21. The memory device of claim 20, wherein at least a portion of the charge storage mediums of two or more said substantially vertically aligned memory elements are common.

22. The memory device of claim 21, wherein the charge storage medium of at least one of said memory elements comprises nanocrystals.

23. The memory device of claim 20, wherein the control gate of at least one of said memory elements comprises a metal conductor.

24. The memory device of claim 20, wherein the charge storage medium of at least one of said memory elements comprises an ONO stack.

25. The memory device of claim 20, wherein the charge storage medium of at least one of said memory elements comprises a floating gate.

26. The memory device of claim 20, at least one of said memory elements further comprising a vertical semiconductor region horizontally disposed relative to said a charge storage medium, wherein said vertical semiconductor region comprises a semiconductor material selected from a group consisting of a polycrystalline semiconductor material and an amorphous semiconductor material.

27. The memory device of claim 26, wherein the charge storage medium comprises an ONO stack.

28. The memory device of claim 27, wherein said charge storage medium further includes an alumina layer, said vertical semiconductor region has a substantially circular shape when viewed from above, and said control gate comprises a metal conductor.

29. The memory device of claim 20, wherein the driver circuitry is at least partially in the silicon substrate and below the plurality of memory elements.

30. The memory device of claim 21, further comprising a conductor disposed between vertically aligned memory elements of the two or more memory device level.