Replacement gate electrode with planar work function material layers

• US 8,853,788 B2
• Filed: 10/21/2013
• Issued: 10/07/2014
• Est. Priority Date: 07/20/2011
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Guo, Dechao, Han, Shu-Jen, Wong, Keith Kwong Hon, Yuan, Jun
• Primary Examiner(s): MUNOZ, ANDRES F
• Application Number:
  US14/058,774
• Publication Number:
  US 20140042561A1
• Time in Patent Office: 351 Days
• Field of Search: None
• US Class Current: 257/369
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/4958 with a multiple layer structure
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

In a replacement gate scheme, a continuous material layer is deposited on a bottom surface and a sidewall surface in a gate cavity. A vertical portion of the continuous material layer is removed to form a gate component of which a vertical portion does not extend to a top of the gate cavity. The gate component can be employed as a gate dielectric or a work function material portion to form a gate structure that enhances performance of a replacement gate field effect transistor.

Claims

1. A semiconductor structure comprising:

a planarization dielectric layer having a planar topmost surface and located on a semiconductor substrate;

a first gate stack comprising;

a U-shaped gate dielectric located on a bottom and sidewalls of a first gate cavity laterally surrounded by said planarization dielectric layer and located in a first device region of said semiconductor substrate;

a first planar work function material portion comprising a first metallic material having a first work function and present on a horizontal portion of said U-shaped gate dielectric;

a second planar work function material portion present on said first planar work function material portion, said second planar work function material portion comprising a second metallic material having a second work function different from said first metallic material and having a topmost surface that is recessed from said planar topmost surface of said planarization dielectric layer; and

a metal portion present on said topmost surface of said second planar work function material portion, said metal portion having a top surface that is coplanar with said planar topmost surface of said planarization dielectric layer; and

a second gate stack comprising;

another U-shaped gate dielectric located on a bottom and sidewalls of a second gate cavity laterally surrounded by said planarization dielectric layer and located in a second device region of said semiconductor substrate;

another second planar work function material portion present on a horizontal portion of said another U-shaped gate dielectric, said another second planar work function material portion having a topmost surface that is recessed from said planar topmost surface of said planarization dielectric layer, and

another metal portion present on said topmost surface of said another second planar work function material portion, said another metal portion having a top surface that is coplanar with said planar topmost surface of said planarization dielectric layer.

2. The semiconductor structure of claim 1, wherein each of said first and said second planar work function material portions has a uniform thickness between one inner vertical sidewall of said U-shaped gate dielectric and another inner vertical sidewall of said U-shaped gate dielectric, and wherein said another second planar work function material portion has a uniform thickness between one inner vertical sidewall of said another U-shaped gate dielectric and another inner vertical sidewall of said another U-shaped gate dielectric.

3. The semiconductor structure of claim 1, wherein said first metallic material is selected from Pt, Rh, Ir, Ru, Cu, Os, Be, Co, Pd, Te, Cr, Ni, TiN, a stack thereof, a conductive oxide thereof, a conductive nitride thereof, an alloy thereof, and a combination thereof, and wherein said second metallic material is selected from Hf, Ti, Zr, Cd, La, Tl, Yb, Al, Ce, Eu, Li, Pb, Tb, Bi, In, Lu, Nb, Sm, V, Zr, Ga, Mg, Gd, Y, TiAl, TaN, a stack thereof, a conductive oxide thereof, a conductive nitride thereof, an alloy thereof, and a combination thereof.

4. The semiconductor structure of claim 1, wherein each of said U-shaped gate dielectric and said another U-shaped gate dielectric includes the horizontal portion and a vertical portion that contiguously extends from said horizontal portion to said planar topmost surface of said planarization dielectric layer.

5. The semiconductor structure of claim 1, wherein said topmost surface of said second planar work function material portion is a horizontal surface that extends from one inner sidewall of said U-shaped gate dielectric to another inner sidewall of said U-shaped gate dielectric, and wherein said topmost surface of said another second planar work function material portion is a horizontal surface that extends from one inner sidewall of said another U-shaped gate dielectric to another inner sidewall of said another U-shaped gate dielectric.

6. The semiconductor structure of claim 1, wherein an entirety of inner sidewalls of said U-shaped gate dielectric contacts sidewalls of said first and said second planar work function material portions and said metal portion, and wherein an entirety of inner sidewalls of said another U-shaped gate dielectric contacts sidewalls of said another second planar work function material portion and said another metal portion.

7. The semiconductor structure of claim 1 further comprising a gate spacer having inner sidewalls that contact outer sidewalls of said U-shaped gate dielectric, and another gate spacer having inner sidewalls that contact outer sidewalls of said another U-shaped gate dielectric.

8. The semiconductor structure of claim 1, wherein sidewalls of said first planar work function material portion and sidewalls of said second planar work function material portion contact a vertical portion of said U-shaped gate dielectric, and wherein sidewalls of said another second planar work function material portion contact a vertical portion of said another U-shaped gate dielectric.

9. The semiconductor structure of claim 1, further comprising:

an embedded stress-generating source region and an embedded stress-generating drain region that are epitaxially aligned to a single crystalline semiconductor material of a body of a field effect transistor in said first device region or a body of another field effect transistor in said second device region.

10. The semiconductor structure of claim 9, further comprising;

a source-side metal semiconductor alloy portion and a drain-side metal semiconductor alloy portion located on said embedded stress-generating source region and said embedded stress-generating drain region, respectively.

11. The semiconductor structure of claim 10, further comprising:

a contact level dielectric material layer located above said planarization dielectric layer.

12. The semiconductor structure of claim 11, further comprising

a source contact via structure and a drain contact via structure embedded in said planarization dielectric layer and said contact level dielectric material layer and contacting said source-side metal semiconductor alloy portion and said drain-side metal semiconductor alloy portion, respectively.

13. The semiconductor structure of claim 1, wherein said semiconductor substrate is a semiconductor-on-insulator substrate.

14. The semiconductor structure of claim 1, wherein said U-shaped gate dielectric and said another U-shaped gate dielectric comprise a dielectric material having a dielectric constant of greater than 8.0.

15. The semiconductor structure of claim 14, wherein said dielectric material having said dielectric constant of greater than 8.0 is selected from the group consisting of HfO₂, ZrO₂, La₂O₃, Al₂O₃, TiO₂, SrTiO₃, LaAlO₃, Y₂O₃, HfO_xN_y, ZrO_xN_y, La₂O_xN_y, Al₂O_xN_y, TiO_xN_y, SrTiO_xN_y, LaAlO_xN_y, Y₂O_xN_y, a silicate thereof, and an alloy thereof, wherein each value of x is independently from 0.5 to 3 and each value of y is independently from 0 to 2.

16. The semiconductor structure of claim 1, wherein said metal portion and said another metal portion include a metal selected from the group consisting of Al, Au, Ag, Cu and W.

17. The semiconductor structure of claim 1, wherein said first metallic material is selected from Hf, Ti, Zr, Cd, La, Tl, Yb, Al, Ce, Eu, Li, Pb, Tb, Bi, In, Lu, Nb, Sm, V, Zr, Ga, Mg, Gd, Y, TiAl, TaN, a stack thereof, a conductive oxide thereof, a conductive nitride thereof, an alloy thereof, and a combination thereof, and wherein said second metallic material is selected from Pt, Rh, Ir, Ru, Cu, Os, Be, Co, Pd, Te, Cr, Ni, TiN, a stack thereof, a conductive oxide thereof, a conductive nitride thereof, an alloy thereof, and a combination thereof.