Integrated circuit package and method of making the same

• US 8,853,836 B1
• Filed: 10/29/2012
• Issued: 10/07/2014
• Est. Priority Date: 06/24/1998
• Status: Expired due to Fees

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: Amkor Technology Incorporated
• Inventors: Glenn, Thomas P.
• Primary Examiner(s): Maldonado, Julio J
• Assistant Examiner(s): BACHNER, ROBERT G
• Application Number:
  US13/662,702
• Time in Patent Office: 708 Days
• Field of Search: 257666-677, 438/121, 438/123, 438/124, 438111-112
• US Class Current: 257/666
• CPC Class Codes: H01L 21/4842 Mechanical treatment, e.g. punching, cutting, deforming, cold welding
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/49503 characterised by the die pad
• CPC Class Codes: H01L 23/49541 Geometry of the lead-frame
• CPC Class Codes: H01L 23/49548 Cross section geometry H01L23/49562 takes precedence
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01037 Rubidium [Rb]
• CPC Class Codes: H01L 2924/01039 Yttrium [Y]
• CPC Class Codes: H01L 2924/01046 Palladium [Pd]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01087 Francium [Fr]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: Y10T 29/49121 : Beam lead frame or beam lead device
• CPC Class Codes: Y10T 29/49126 : Assembling bases
• CPC Class Codes: Y10T 29/4913 : Assembling to base an electrical component, e.g., capacitor, etc.
• CPC Class Codes: Y10T 29/49146 : with encapsulating, e.g., potting, etc.
• CPC Class Codes: Y10T 29/49155 : Manufacturing circuit on or in base
• CPC Class Codes: Y10T 29/49171 : with encapsulating
• CPC Class Codes: Y10T 428/24207 : with strand[s] or strand-portion[s] between layers [e.g., upholstery trim, etc.]

Abstract

Packages for an integrated circuit die and methods and leadframes for making such packages are disclosed. The package includes a die, a die pad, peripheral metal contacts, bond wares, and an encapsulant. The die pad and contacts are located at a lower surface of the package. The die pad and the contacts have side surfaces which include reentrant portions and asperities to engage the encapsulant.

Claims

1. A semiconductor device comprising:

a metal die pad comprising a first planar surface, a second planar surface opposite the first planar surface, and four peripheral edge surfaces that generally extend between the first and second planar surfaces around a perimeter of said die pad;

a plurality of metal contacts;

a semiconductor die coupled to the first planar surface of said die pad and electrically coupled to said plurality of metal contacts;

a molding covering at least said semiconductor die, at least a portion of the first planar surface of said die pad, and a portion of each of said plurality of metal contacts; and

a tie bar extending from a first peripheral edge surface of said die pad, where said tie bar comprises a first edge that runs in a direction generally parallel to the first peripheral edge surface, a second edge that runs in a direction generally diagonal to the first peripheral edge surface, and a severed edge that is at least partially exposed by said molding.

2. The semiconductor device of claim 1, wherein said tie bar extends from only the first peripheral edge surface of said die pad.

3. The semiconductor device of claim 1, wherein said tie bar comprises a third edge that runs in a direction generally perpendicular to the first peripheral edge surface of said die pad.

4. The semiconductor device of claim 1, wherein the second edge of said tie bar is non-linear.

5. The semiconductor device of claim 1, further comprising a second tie bar extending from said die pad, where said second tie bar comprises a first edge that runs in a direction generally parallel to the first peripheral edge surface, a second edge that runs in a direction generally diagonal to the first peripheral edge surface, and a severed edge that is at least partially exposed by said molding.

6. The semiconductor device of claim 5, wherein said second tie bar extends from a second peripheral edge surface of said die pad that is opposite the first peripheral edge surface of said die pad.

7. The semiconductor device of claim 6, wherein said die pad is rectangular-shaped with long and short sides, and the first and second peripheral edge surfaces are at the short sides of said rectangular shape.

8. The semiconductor device of claim 7, wherein said plurality of metal contacts are disposed along only the long sides of said rectangular shape.

9. The semiconductor device of claim 1, wherein a first metal contact of said plurality of metal contacts comprises a first end closest to said die pad, a second end farthest from said die pad, and a linear edge that connects the first end and the second end.

10. The semiconductor device of claim 1, wherein the severed edge of said tie bar is at least partially exposed by said molding at a first end of said molding, and the first end of said molding is free of exposed electrical connections.

11. A semiconductor device comprising:

a metal die pad comprising a first planar surface, a second planar surface opposite the first planar surface, and four peripheral edge surfaces that generally extend between the first and second planar surfaces around a perimeter of said die pad;

a plurality of metal contacts;

a semiconductor die coupled to the first planar surface of said die pad and electrically coupled to said plurality of metal contacts;

a molding covering at least said semiconductor die, at least a portion of the first planar surface of said die pad, and a portion of each of said plurality of metal contacts; and

a tie bar extending from a first peripheral edge surface of said die pad, where said tie bar comprises a first edge that runs in a direction generally parallel to the first peripheral edge surface, a second edge that runs in a direction generally diagonal to the first peripheral edge surface, a third edge that runs in a direction generally perpendicular to the first peripheral edge surface, and a severed edge that is at least partially exposed by said molding.

12. The semiconductor device of claim 11, wherein said tie bar is exposed by said molding at only one side of said molding.

13. The semiconductor device of claim 11, wherein tie bars coupled to said die pad are exposed at only two sides of said molding.

14. The semiconductor device of claim 11, further comprising a second tie bar extending from said die pad, where said second tie bar comprises a first edge that runs in a direction generally parallel to the first peripheral edge surface, a second edge that runs in a direction generally diagonal to the first peripheral edge surface, a third edge that runs in a direction generally perpendicular to the first peripheral edge surface, and a severed edge that is at least partially exposed by said molding.

15. The semiconductor device of claim 14, wherein said second tie bar extends from a second peripheral edge surface of said die pad that is opposite the first peripheral edge surface of said die pad.

16. The semiconductor device of claim 11, wherein the second edge of said tie bar is non-linear.

17. The semiconductor device of claim 11, wherein a first metal contact of said plurality of metal contacts comprises a first end closest to said die pad, a second end farthest from said die pad, and a linear edge that connects the first end and the second end.

18. A semiconductor device comprising:

a metal die pad comprising a first planar surface, a second planar surface opposite the first planar surface, and four peripheral edge surfaces that generally extend between the first and second planar surfaces around a perimeter of said die pad;

a plurality of metal contacts;

a semiconductor die coupled to the first planar surface of said die pad and electrically coupled to said plurality of metal contacts;

a molding covering at least said semiconductor die, at least a portion of the first planar surface of said die pad, and a portion of each of said plurality of metal contacts; and

at least one tie bar extending from a first peripheral edge surface of said die pad, where said at least one tie bar comprises a first edge that runs in a direction generally parallel to the first peripheral edge surface, a second edge that runs in a direction generally parallel to the first peripheral edge surface, a third edge that runs in a direction generally diagonal to the first peripheral edge surface, a fourth edge that runs in a direction generally diagonal to the first peripheral edge surface, and a severed edge that is at least partially exposed by said molding.

19. The semiconductor device of claim 18, wherein the third edge of said at least one tie bar and the fourth edge of said at least one tie bar generally run in different respective diagonal directions.

20. The semiconductor device of claim 19, wherein the first edge of said at least one tie bar is on a first side of a longitudinal centerline of said die pad, and the second edge of said at least one tie bar is on a second side of the longitudinal centerline of said die pad.

21. The semiconductor device of claim 20, wherein said at least one tie bar is a single tie bar that extends from the first peripheral edge surface along the longitudinal centerline of said die pad.

22. The semiconductor device of claim 18, wherein the first edge of said at least one tie bar meets the third edge of said at least one tie bar, and the second edge of said at least one tie bar meets the fourth edge of said at least one tie bar.

23. The semiconductor device of claim 18 wherein said at least one tie bar extends from only the first peripheral edge surface of said die pad.