Voltage level shifter

• US 8,854,104 B2
• Filed: 03/11/2013
• Issued: 10/07/2014
• Est. Priority Date: 12/31/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chung, Tao Wen, Chern, Chan-Hong, Huang, Tsung-Ching (Jim), Lin, Chih-Chang, Huang, Ming-Chieh
• Primary Examiner(s): Wells, Kenneth B.
• Application Number:
  US13/793,681
• Publication Number:
  US 20140184299A1
• Time in Patent Office: 575 Days
• Field of Search: 327/333, 326/80, 326/81
• US Class Current: 327/333
• CPC Class Codes: H03K 17/102 in field-effect transistor switches
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS
• CPC Class Codes: H03K 3/356182 with additional means for controlling the main nodes
• CPC Class Codes: H03L 5/00 Automatic control of voltage, current, or power

Abstract

A circuit includes a first capacitive device and a first latch. The first capacitive device includes a first end configured to receive a first input signal and a second end coupled with the first latch. The first latch includes a first transistor and a second transistor that are of a first type. A first terminal of the first transistor and a first terminal of the second transistor are each configured to receive a first voltage value. A second terminal of the first transistor is coupled with a third terminal of the second transistor. A third terminal of the first transistor is coupled with a second terminal of the second transistor and with the second end of the capacitive device, and is configured to provide an output voltage for the first latch.

Claims

1. A circuit comprising:

a first capacitive device;

a first latch;

a second capacitive device;

a second latch; and

a first circuit,

wherein

the first capacitive device includes a first end and a second end;

the first end is configured to receive a first input signal;

the first latch includes a first transistor and a second transistor;

the first transistor and the second transistor are of a first type;

a first terminal of the first transistor and a first terminal of the second transistor are configured to receive a first voltage value;

a second terminal of the first transistor is coupled with a third terminal of the second transistor;

a third terminal of the first transistor is coupled with a second terminal of the second transistor and with the second end of the capacitive device, and is configured to provide an output voltage for the first latch;

the second capacitive device includes a first end and a second end;

the first end of the second capacitive device is configured to receive the first input signal;

the second latch includes a third transistor and a fourth transistor;

the third transistor and the fourth transistor are of a second type different from the first type;

the second end of the second capacitive device is coupled with the second latch; and

the first circuit is coupled between the second end of the first capacitive device and the second end of the second capacitive device.

2. The circuit of claim 1, wherein

the first type is a P-type;

the first input signal swings between a second voltage value and a third voltage value; and

the third voltage value is higher than the second voltage value and is lower than the first voltage value.

3. The circuit of claim 2, wherein

based on the first input signal, the first capacitive device is configured to generate a second input signal at the second end of the first capacitive device;

and

the second input signal swings between the third voltage value and the first voltage value.

4. The circuit of claim 1, wherein

the first type is an N-type;

the first input signal swings between a second voltage value and a third voltage value;

the second voltage value is substantially equal to the first voltage value; and

the third voltage value is higher than the second voltage value.

5. The circuit of claim 4, wherein

based on the first input signal, the first capacitive device is configured to generate a second input signal at the second end of the first capacitive device;

and

the second input signal swings between the second voltage value and the third voltage value.

6. The circuit of claim 1, wherein

a first terminal of the third transistor and a first terminal of the fourth transistor are configured to receive a second voltage value different from the first voltage value;

a second terminal of the third transistor is coupled with a third terminal of the fourth transistor; and

a third terminal of the third transistor is coupled with a second terminal of the fourth transistor and with the second end of the second capacitive device, and is configured to provide an output voltage for the second latch.

7. The circuit of claim 6, wherein

the first type is P-type;

the second type is N-type;

the first input signal swings between the second voltage value and a third voltage value; and

the third voltage value is higher than the second voltage value and is lower than the first voltage value.

8. The circuit of claim 6, wherein

the first input signal swings between the second voltage value and a third voltage value;

based on the first input signal, the second capacitive device is configured to generate a third input signal at the second end of the second capacitive device; and

the third input signal swings between the second voltage value and the third voltage value.

9. The circuit of claim 6, wherein

the first circuit include a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor;

a first terminal of the fifth transistor is coupled with the second end of the first capacitive device;

a second terminal of the fifth transistor, of the sixth transistor, of the seventh transistor, and of the eighth transistor are each configured to receive a bias voltage;

a third terminal of the fifth transistor is coupled with a third terminal of the seventh transistor;

a first terminal of the sixth transistor is coupled with the third terminal of the second transistor;

a third terminal of the sixth transistor is coupled with a third terminal of the eighth transistor, and is configured to provide an output voltage for the first circuit;

a first terminal of the seventh transistor is coupled with the second end of the second capacitive device; and

a first terminal of the eighth transistor is coupled with the third terminal of the fourth transistor.

10. The circuit of claim 6, wherein

the first circuit includes at least one first diode and at least one second diode;

the at least one first diode is coupled between the second end of the first capacitive device and the second end of the second capacitive device; and

the at least one second diode is coupled between the third terminal of the second transistor and the third terminal of the fourth transistor.

11. The circuit of claim 6 further comprising a second circuit, wherein

the second circuit comprises a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor;

a first terminal of the fifth transistor is configured to receive the first voltage value;

a second terminal of the fifth transistor is configured to receive the output voltage of the first latch;

a third terminal of the fifth transistor is coupled with a first terminal of the sixth transistor;

a second terminal of the fifth transistor and of the sixth transistor are each configured to receive a second bias voltage;

a third terminal of the sixth transistor and of the seventh transistor are coupled together, and are configured to provide an output voltage for the third circuit;

a first terminal of the seventh transistor is coupled with a third terminal of the eighth transistor;

a first terminal of the eighth transistor is configured to receive the second voltage value; and

a second terminal of the eighth transistor is configured to receive the output voltage of the second latch.

12. A circuit comprising:

a first capacitive device;

a second capacitive device;

at least one pre-driver circuit; and

a post driver circuit,

wherein

the first capacitive device is configured to receive an input signal and to generate a first capacitive output signal, wherein the first input signal swings between a first voltage level and a second voltage level higher than the first voltage level, the first capacitive output signal swings between a third voltage level and a fourth voltage level, the third voltage level is higher than the first voltage level, and the fourth voltage level is higher than the third voltage level;

the second capacitive device is configured to receive the input signal and to generate a second capacitive output signal, wherein the second capacitive output signal swings between a fifth voltage level and a sixth voltage level, the fifth voltage level is substantially the same as the first voltage level, and the sixth voltage level is higher than the fifth voltage level;

the at least one pre-driver circuit is configured to receive the first capacitive output signal and to generate a first pre-driver output signal, wherein the first pre-driver output signal swings between a seventh voltage level and an eighth voltage level, the seventh voltage level is substantially the same as the third voltage level and the eighth voltage level is substantially the same as the fourth voltage level;

the at least one pre-driver circuit is configured to receive the second capacitive output signal and to generate a second pre-driver output signal, wherein the second pre-driver output signal swings between a ninth voltage level and a tenth voltage level, the ninth voltage level is substantially the same as the fifth voltage level and the tenth voltage level is substantially the same as the sixth voltage level;

the post driver circuit is configured to receive the first pre-driver output signal and the second pre-driver output signal, and to generate a post-driver output signal, wherein the post-driver output signal swings between an eleventh voltage level and a twelfth voltage level, the eleventh voltage level is substantially the same as the first voltage level and the twelfth voltage level is substantially the same as the fourth voltage level;

a pre-driver circuit of the at least one pre-driver circuit includes a first latch, a first circuit, and a second latch; and

the first circuit is coupled between the first latch and the second latch.

13. The circuit of claim 12, wherein

if the at least one pre-driver circuit has more than one pre-driver circuit, sizes of transistors in a first pre-driver circuit are smaller than sizes of transistors in a second pre-driver circuit;

and

the first pre-driver circuit drives the second pre-driver circuit.

14. The circuit of claim 12, wherein

the first latch has a first transistor of a first type and a second transistor of the first type;

the second latch has a first transistor of a second type and a second transistor of the second type;

a first terminal of the first-type first transistor and a first terminal of the first-type second transistor are each configured to receive a first supply voltage value;

a second terminal of the first-type first transistor is coupled with a third terminal of the first-type second transistor, and with a second terminal of the first circuit;

a third terminal of the first-type first transistor is coupled with a first terminal of the first circuit, and with a second terminal of the first-type second transistor, and is configured to generate an output voltage for the first latch;

a first terminal of the second-type first transistor and a first terminal of the second-type second transistor are each configured to receive a second supply voltage value;

a second terminal of the second-type first transistor is coupled with a third terminal of the second-type second transistor, and with a fourth terminal of the first circuit; and

a third terminal of the second-type first transistor is coupled with a third terminal of the first circuit and with a second terminal of the second-type second transistor, and is configured to generate an output voltage for the second latch.

15. The circuit of claim 12, wherein the post driver comprises:

a transistor of the first type, a gate of the transistor of the first type being configured to receive the first pre-driver output signal; and

a transistor of the second type, a gate of the transistor of the second type being configured to receive the second pre-driver output signal.

16. The circuit of claim 15, wherein

the gate of the transistor of the first type of the post driver is electrically coupled to a node of the first capacitive device, the node of the first capacitive device being configured to carry the first capacitive output signal;

and

the gate of the transistor of the second type of the post driver is electrically couple to a node of the second capacitive device, the node of the second capacitive device being configured to carry the second capacitive output signal.

17. A circuit comprising:

a first latch having a first transistor of a first type and a second transistor of the first type;

a second latch having a first transistor of a second type and a second transistor of the second type; and

a first circuit,

wherein

a first terminal of the first-type first transistor and a first terminal of the first-type second transistor are each configured to receive a first voltage value;

a second terminal of the first-type first transistor is coupled with a third terminal of the first-type second transistor, and with a second terminal of the first circuit;

a third terminal of the first-type first transistor is coupled with a first terminal of the first circuit, and with a second terminal of the first-type second transistor, and is configured to generate an output voltage for the first latch;

a first terminal of the second-type first transistor and a first terminal of the second-type second transistor are each configured to receive a second voltage value;

a second terminal of the second-type first transistor is coupled with a third terminal of the second-type second transistor, and with a fourth terminal of the first circuit; and

a third terminal of the second-type first transistor is coupled with a third terminal of the first circuit and with a second terminal of the second-type second transistor, and is configured to generate an output voltage for the second latch.

18. The circuit of claim 17 further comprising a first capacitive device and a second capacitive device,

wherein

the first capacitive device is coupled with the first terminal of the first circuit;

and

the second capacitive device is coupled with the second terminal of the first circuit.

19. The circuit of claim 18, further comprising a third transistor of the first type, a fourth transistor of the first type, a third transistor of the second type, and a fourth transistor of the second type,

wherein

a first terminal of the first-type third transistor is configured to receive the first voltage value;

a second terminal of the first-type third transistor is configured to receive the output voltage of the first latch;

a third terminal of the first-type third transistor is coupled with a first terminal of the first-type fourth transistor;

a second terminal of the first-type fourth transistor and a second terminal of the second-type fourth transistor are each configured to receive a bias voltage;

a third terminal of the first-type fourth transistor is coupled with a third terminal of the second-type fourth transistor;

a first terminal of the second-type fourth transistor is coupled with a third terminal of the second-type third transistor;

a first terminal of the second-type third transistor is configured to receive the second voltage value; and

a second terminal of the second-type third transistor is configured to receive the output voltage of the second latch.

20. The circuit of claim 17, wherein

the first capacitive device and the second capacitive device are each configured to receive an input signal;

the input signal swings between a third voltage value and a fourth voltage value higher than the third voltage value;

the first voltage value is higher than the fourth voltage value; and

the second voltage value is substantially the same as the third voltage value.