Voltage level shifter
First Claim
1. A circuit comprising:
- a first capacitive device;
a first latch;
a second capacitive device;
a second latch; and
a first circuit,whereinthe first capacitive device includes a first end and a second end;
the first end is configured to receive a first input signal;
the first latch includes a first transistor and a second transistor;
the first transistor and the second transistor are of a first type;
a first terminal of the first transistor and a first terminal of the second transistor are configured to receive a first voltage value;
a second terminal of the first transistor is coupled with a third terminal of the second transistor;
a third terminal of the first transistor is coupled with a second terminal of the second transistor and with the second end of the capacitive device, and is configured to provide an output voltage for the first latch;
the second capacitive device includes a first end and a second end;
the first end of the second capacitive device is configured to receive the first input signal;
the second latch includes a third transistor and a fourth transistor;
the third transistor and the fourth transistor are of a second type different from the first type;
the second end of the second capacitive device is coupled with the second latch; and
the first circuit is coupled between the second end of the first capacitive device and the second end of the second capacitive device.
1 Assignment
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Accused Products
Abstract
A circuit includes a first capacitive device and a first latch. The first capacitive device includes a first end configured to receive a first input signal and a second end coupled with the first latch. The first latch includes a first transistor and a second transistor that are of a first type. A first terminal of the first transistor and a first terminal of the second transistor are each configured to receive a first voltage value. A second terminal of the first transistor is coupled with a third terminal of the second transistor. A third terminal of the first transistor is coupled with a second terminal of the second transistor and with the second end of the capacitive device, and is configured to provide an output voltage for the first latch.
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Citations
20 Claims
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1. A circuit comprising:
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a first capacitive device; a first latch; a second capacitive device; a second latch; and a first circuit, wherein the first capacitive device includes a first end and a second end; the first end is configured to receive a first input signal; the first latch includes a first transistor and a second transistor; the first transistor and the second transistor are of a first type; a first terminal of the first transistor and a first terminal of the second transistor are configured to receive a first voltage value; a second terminal of the first transistor is coupled with a third terminal of the second transistor; a third terminal of the first transistor is coupled with a second terminal of the second transistor and with the second end of the capacitive device, and is configured to provide an output voltage for the first latch; the second capacitive device includes a first end and a second end; the first end of the second capacitive device is configured to receive the first input signal; the second latch includes a third transistor and a fourth transistor; the third transistor and the fourth transistor are of a second type different from the first type; the second end of the second capacitive device is coupled with the second latch; and the first circuit is coupled between the second end of the first capacitive device and the second end of the second capacitive device. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A circuit comprising:
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a first capacitive device; a second capacitive device; at least one pre-driver circuit; and a post driver circuit, wherein the first capacitive device is configured to receive an input signal and to generate a first capacitive output signal, wherein the first input signal swings between a first voltage level and a second voltage level higher than the first voltage level, the first capacitive output signal swings between a third voltage level and a fourth voltage level, the third voltage level is higher than the first voltage level, and the fourth voltage level is higher than the third voltage level; the second capacitive device is configured to receive the input signal and to generate a second capacitive output signal, wherein the second capacitive output signal swings between a fifth voltage level and a sixth voltage level, the fifth voltage level is substantially the same as the first voltage level, and the sixth voltage level is higher than the fifth voltage level; the at least one pre-driver circuit is configured to receive the first capacitive output signal and to generate a first pre-driver output signal, wherein the first pre-driver output signal swings between a seventh voltage level and an eighth voltage level, the seventh voltage level is substantially the same as the third voltage level and the eighth voltage level is substantially the same as the fourth voltage level; the at least one pre-driver circuit is configured to receive the second capacitive output signal and to generate a second pre-driver output signal, wherein the second pre-driver output signal swings between a ninth voltage level and a tenth voltage level, the ninth voltage level is substantially the same as the fifth voltage level and the tenth voltage level is substantially the same as the sixth voltage level; the post driver circuit is configured to receive the first pre-driver output signal and the second pre-driver output signal, and to generate a post-driver output signal, wherein the post-driver output signal swings between an eleventh voltage level and a twelfth voltage level, the eleventh voltage level is substantially the same as the first voltage level and the twelfth voltage level is substantially the same as the fourth voltage level; a pre-driver circuit of the at least one pre-driver circuit includes a first latch, a first circuit, and a second latch; and the first circuit is coupled between the first latch and the second latch. - View Dependent Claims (13, 14, 15, 16)
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17. A circuit comprising:
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a first latch having a first transistor of a first type and a second transistor of the first type; a second latch having a first transistor of a second type and a second transistor of the second type; and a first circuit, wherein a first terminal of the first-type first transistor and a first terminal of the first-type second transistor are each configured to receive a first voltage value; a second terminal of the first-type first transistor is coupled with a third terminal of the first-type second transistor, and with a second terminal of the first circuit; a third terminal of the first-type first transistor is coupled with a first terminal of the first circuit, and with a second terminal of the first-type second transistor, and is configured to generate an output voltage for the first latch; a first terminal of the second-type first transistor and a first terminal of the second-type second transistor are each configured to receive a second voltage value; a second terminal of the second-type first transistor is coupled with a third terminal of the second-type second transistor, and with a fourth terminal of the first circuit; and a third terminal of the second-type first transistor is coupled with a third terminal of the first circuit and with a second terminal of the second-type second transistor, and is configured to generate an output voltage for the second latch. - View Dependent Claims (18, 19, 20)
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Specification