Liquid crystal display device and electronic device including the liquid crystal display device

• US 8,854,286 B2
• Filed: 10/08/2010
• Issued: 10/07/2014
• Est. Priority Date: 10/16/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Arasawa, Ryo, Koyama, Jun, Tsubuku, Masashi, Noda, Kosei
• Primary Examiner(s): CERULLO, LILIANA P
• Application Number:
  US12/901,023
• Publication Number:
  US 20110090183A1
• Time in Patent Office: 1,460 Days
• Field of Search: 345 87-101, 257/43, 257/41, 257 76- 78, 257 57- 72, 349/141
• US Class Current: 345/92
• CPC Class Codes: G02F 1/133553 Reflecting elements associated to illuminating devices G02F1/133605
• CPC Class Codes: G02F 1/13439 characterised by their electrical, optical, physical properties; materials therefor; method of making
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2201/123 pixel
• CPC Class Codes: G02F 2202/10 semiconductor
• CPC Class Codes: G09G 2300/08 Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 3/3614 Control of polarity reversal in general
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02266 deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 21/467 using masks
• CPC Class Codes: H01L 21/477 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/38 - H01L21/449 and H01L21/461 - H01L21/475 take precedence
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 29/24 : including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/42356 : Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/45 : Ohmic electrodes
• CPC Class Codes: H01L 29/66969 : of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78648 : arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7869 : having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

In a liquid crystal display device including a plurality of pixels in a display portion and configured to performed display in a plurality of frame periods, each of the frame periods includes a writing period and a holding period, and after an image signal is input to each of the plurality of pixels in the writing period, a transistor included in each of the plurality of pixels is turned off and the image signal is held for at least 30 seconds in the holding period. The pixel includes a semiconductor layer including an oxide semiconductor layer, and the oxide semiconductor layer has a carrier concentration of less than 1×10¹⁴/cm³.

Claims

1. A method for driving a liquid crystal display device comprising a plurality of pixels in a display portion and configured to perform display in a plurality of frame periods,

wherein each of the plurality of frame periods includes a writing period and a holding period,

wherein after an image signal is input to each of the plurality of pixels in the writing period, a transistor included in each of the plurality of pixels is turned off and the image signal is held for at least 30 seconds in the holding period,

wherein the transistor comprises a semiconductor layer including an oxide semiconductor,

wherein a concentration of hydrogen in the oxide semiconductor, which is measured by secondary ion mass spectrometry, is 5×

10¹⁹/cm³ or less, and

wherein the display portion includes a liquid crystal layer comprising any one selected from a twisted nematic (TN) mode, an in-plane-switching (IPS) mode, a fringe field switching (FFS) mode, an axially symmetric aligned micro-cell (ASM) mode, an optical compensated birefringence (OCB) mode, a vertical alignment (VA) mode and a blue phase.

2. The method for driving the liquid crystal display device according to claim 1, wherein the image signal is held for 1 minute or longer and shorter than 10 minutes in the holding period.

3. The method for driving the liquid crystal display device according to claim 1, wherein the oxide semiconductor has a carrier concentration of less than 1×

10¹⁴/cm³.

4. The method for driving the liquid crystal display device according to claim 1,

wherein a current per micrometer of a channel width of the semiconductor layer is 1×

10<sup>−

17</sup> A or less by applying a voltage in a range of 1 V to 10 V to a portion of the semiconductor layer and a voltage in a range of −

5 V to −

20 V to a gate of the transistor.

5. The method for driving the liquid crystal display device according to claim 1, wherein the liquid crystal display device is included in an electronic device.

6. A method for driving a liquid crystal display device comprising a plurality of pixels in a display portion and configured to perform display in a plurality of frame periods,

wherein each of the plurality of frame periods includes a writing period and a holding period, and

wherein after an image signal is input to each of the plurality of pixels in the writing period, a transistor included in each of the plurality of pixels is turned off and the image signal is held for at least 30 seconds in the holding period, and

wherein the display portion includes a liquid crystal layer comprising any one selected from a twisted nematic (TN) mode, an in-plane-switching (IPS) mode, a fringe field switching (FFS) mode, an axially symmetric aligned micro-cell (ASM) mode, an optical compensated birefringence (OCB) mode, a vertical alignment (VA) mode and a blue phase.

7. The method for driving the liquid crystal display device according to claim 6, wherein the image signal is held for 1 minute or longer and shorter than 10 minutes in the holding period.

8. The method for driving the liquid crystal display device according to claim 6, wherein the transistor comprises a semiconductor layer including an oxide semiconductor, and the oxide semiconductor has a carrier concentration of less than 1×

10¹⁴/cm³.

9. The method for driving the liquid crystal display device according to claim 8, wherein a current per micrometer of a channel width of the semiconductor layer is 1×

10<sup>−

17</sup> A or less by applying a voltage in a range of 1V to 10 V to a portion of the semiconductor layer and a voltage in a range of −

5 V to −

20 V to a gate of the transistor.

10. The method for driving the liquid crystal display device according to claim 6, wherein the liquid crystal display device is included in an electronic device.

11. A method for driving a liquid crystal display device comprising a plurality of pixels in a display portion and configured to perform display in a plurality of frame periods,

wherein each of the plurality of frame periods includes a writing period and a holding period,

wherein after an image signal with a voltage whose polarity is inverted a plurality of times is input to each of the plurality of pixels in the writing period, a transistor included in each of the plurality of pixels is turned off and the image signal is held for at least 30 seconds in the holding period, and

wherein the display portion includes a liquid crystal layer comprising any one selected from a twisted nematic (TN) mode, an in-plane-switching (IPS) mode, a fringe field switching (FFS) mode, an axially symmetric aligned micro-cell (ASM) mode, an optical compensated birefringence (OCB) mode, a vertical alignment (VA) mode and a blue phase.

12. The liquid crystal display device according to claim 11, wherein a polarity of the voltage of the image signal held at each of the plurality of pixels in the holding period is a polarity of the voltage supplied at the end of the writing period.

13. The method for driving the liquid crystal display device according to claim 11, wherein the image signal is held for 1 minute or longer and shorter than 10 minutes in the holding period.

14. The liquid crystal display device according to claim 11, wherein the transistor comprises a semiconductor layer including an oxide semiconductor, and the oxide semiconductor has a carrier concentration of less than 1×

10¹⁴/cm³.

15. The liquid crystal display device according to claim 14,

wherein a current per micrometer of a channel width of the semiconductor layer is 1×

10<sup>−

17</sup> A or less by applying a voltage in a range of 1 V to 10 V to a portion of the semiconductor layer and a gate voltage in a range of −

5 V to −

20 V to a gate of the transistor.

16. An electronic device comprising the liquid crystal display device according to claim 11.