Memory device and driving method of the memory device
First Claim
1. A memory device comprising:
- a pair of inverters, wherein an output terminal of one of the phase inversion elements inverters is connected to an input terminal of the other of the inverters, wherein the pair of inverters is configured to hold data when power is supplied;
a capacitor;
a first transistor between the output terminal of the one of the inverters and a terminal, wherein the first transistor is configured to transmit the data between the terminal and the pair of inverters;
a second transistor provided above at least one of the inverters, wherein the second transistor is configured to control a flow of charges between the output terminal of the one of the inverters and the capacitor; and
a circuit, wherein the circuit is configured to set the output terminal of the one of the inverters and an output terminal of the other of the inverters to a first potential.
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Accused Products
Abstract
A memory device which can reduce power consumption and a driving method thereof are disclosed. In a memory element including an inverter and the like, a capacitor for holding data and a capacitor switching element for controlling store and release of charge in the capacitor are provided. The capacitor switching element is designed so that the off-state current is sufficiently low. Therefore, even when power supply of the inverter is stopped after charge corresponding to data is stored in the capacitor, data can be held for a long period of time. In order to return data, potentials of output and input terminals of the inverter are set to a precharge potential, then charge in the capacitor is released, and power is supplied to the inverter. A switching element for supplying the precharge potential may be provided.
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Citations
20 Claims
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1. A memory device comprising:
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a pair of inverters, wherein an output terminal of one of the phase inversion elements inverters is connected to an input terminal of the other of the inverters, wherein the pair of inverters is configured to hold data when power is supplied; a capacitor; a first transistor between the output terminal of the one of the inverters and a terminal, wherein the first transistor is configured to transmit the data between the terminal and the pair of inverters; a second transistor provided above at least one of the inverters, wherein the second transistor is configured to control a flow of charges between the output terminal of the one of the inverters and the capacitor; and a circuit, wherein the circuit is configured to set the output terminal of the one of the inverters and an output terminal of the other of the inverters to a first potential. - View Dependent Claims (2, 3, 4, 5, 16)
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6. A memory device comprising:
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a pair of inverters, wherein an output terminal of one of the inverters is connected to an input terminal of the other of the inverters, wherein the pair of inverters is configured to hold data when power of supplied; a capacitor; a first switching element provided above at least one of the inverters, wherein the first switching element is configured to control a flow of charges between the output terminal of the one of the inverters and the capacitor; a second switching element between input terminals of the pair of inverters; and a circuit, wherein the circuit is configured to supply a first potential to the input terminal of the one of the inverters. - View Dependent Claims (7, 8, 9, 10, 17, 19)
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11. A memory device comprising:
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a memory element comprising; a pair of inverters, wherein an output terminal of one of the inverters is connected to an input terminal of the other of the inverters, wherein the pair of inverters is configured to hold data when power is supplied; a capacitor; and a first switching element provided above at least one of the inverters, wherein the first switching element is configured to controls a flow of charges between the output terminal of the one of the inverters and the capacitor; and a second switching element connected to an output terminal of the memory element, wherein the second switching element is configured to control the potential of the output terminal of the memory element. - View Dependent Claims (12, 13, 14, 15, 18, 20)
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Specification