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Memory device and driving method of the memory device

  • US 8,854,867 B2
  • Filed: 04/09/2012
  • Issued: 10/07/2014
  • Est. Priority Date: 04/13/2011
  • Status: Active Grant
First Claim
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1. A memory device comprising:

  • a pair of inverters, wherein an output terminal of one of the phase inversion elements inverters is connected to an input terminal of the other of the inverters, wherein the pair of inverters is configured to hold data when power is supplied;

    a capacitor;

    a first transistor between the output terminal of the one of the inverters and a terminal, wherein the first transistor is configured to transmit the data between the terminal and the pair of inverters;

    a second transistor provided above at least one of the inverters, wherein the second transistor is configured to control a flow of charges between the output terminal of the one of the inverters and the capacitor; and

    a circuit, wherein the circuit is configured to set the output terminal of the one of the inverters and an output terminal of the other of the inverters to a first potential.

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