Configuring storage cells

• US 8,854,882 B2
• Filed: 10/30/2013
• Issued: 10/07/2014
• Est. Priority Date: 01/27/2010
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Intelligent Intellectual Property Holdings LLC
• Inventors: Strasser, John, Flynn, David, Fillingim, Jeremy, Wood, Robert
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US14/067,323
• Publication Number:
  US 20140056068A1
• Time in Patent Office: 342 Days
• Field of Search: 365/185.03, 365/185.09, 365/185.11, 365/185.12, 365/185.18, 365/185.24, 365/185.29, 365/185.33
• US Class Current: 365/185.03
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/00 Erasable programmable read-only memories G11C14/00 takes precedence
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/026 in sense amplifiers
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/50016 of retention

Abstract

Apparatuses, systems, methods, and computer program products are disclosed for configuring storage cells. A method includes detecting a shift in a read voltage level past a read voltage threshold for a set of memory cells of a non-volatile memory medium. A method includes adjusting a read voltage threshold for the set of memory cells by an amount based at least in part on one or more characteristics of the set of memory cells in response to the shift in the read voltage level. A method includes configuring the set of memory cells to use the adjusted read voltage threshold.

Claims

1. An apparatus comprising:

a data set read module configured to detect a shift in a read voltage level past a read voltage threshold for a set of memory cells of a non-volatile memory medium;

an adjustment module configured to, in response to the shift in the read voltage level, adjust a read voltage threshold for the set of memory cells by an amount based at least in part on one or more characteristics of the set of memory cells; and

a read voltage module configured to configure the set of memory cells to use the adjusted read voltage threshold.

2. The apparatus of claim 1, further comprising a persistence module configured to retain the adjusted read voltage threshold for the set of memory cells.

3. The apparatus of claim 2, wherein the persistence module is configured to store different read voltage thresholds for different sub-groupings of the set of memory cells.

4. The apparatus of claim 3, wherein the read voltage module is configured to reconfigure the entire set of memory cells to use one of the different read voltage thresholds in response to a read request for a sub-grouping associated with the one of the different read voltage thresholds.

5. The apparatus of claim 2, wherein the persistence module is configured to send the adjusted read voltage threshold to the non-volatile memory medium for each read operation for the set of storage cells.

6. The apparatus of claim 1, wherein the one or more characteristics include one or more of a usage history for the set of memory cells, an error history for the set of memory cells, an age for the set of memory cells, a number of program and erase cycles for the set of memory cells, and an amount of wear for the set of memory cells.

7. The apparatus of claim 1, wherein the data set read module is further configured to detect the shift in the read voltage level by detecting a data error for the set of memory cells.

8. The apparatus of claim 1, wherein the data set read module is further configured to detect the shift in the read voltage level in response to a testing operation for the set of memory cells.

9. An apparatus comprising:

means for detecting a shift in a read voltage level past a read voltage threshold for a set of memory cells of a non-volatile memory medium;

means for adjusting a read voltage threshold for the set of memory cells by an amount based at least in part on one or more characteristics of the set of memory cells in response to the shift in the read voltage level; and

means for configuring the set of memory cells to use the adjusted read voltage threshold.

10. The apparatus of claim 9, further comprising means for retaining the adjusted read voltage threshold for the set of memory cells.

11. The apparatus of claim 9, further comprising means for storing different read voltage thresholds for different sub-groupings of the set of memory cells.

12. The apparatus of claim 9, further comprising means for reconfiguring the entire set of memory cells to use one of the different read voltage thresholds in response to a read request for a sub-grouping associated with the one of the different read voltage thresholds.

13. The apparatus of claim 9, further comprising means for sending the adjusted read voltage threshold to the non-volatile memory medium for each read operation for the set of storage cells.

14. A method comprising:

detecting a shift in a read voltage level past a read voltage threshold for a set of memory cells of a non-volatile memory medium;

adjusting a read voltage threshold for the set of memory cells by an amount based at least in part on one or more characteristics of the set of memory cells in response to the shift in the read voltage level; and

configuring the set of memory cells to use the adjusted read voltage threshold.

15. The method of claim 14, further comprising retaining the adjusted read voltage threshold for the set of memory cells.

16. The method of claim 14, further comprising storing different read voltage thresholds for different sub-groupings of the set of memory cells.

17. The method of claim 16, further comprising reconfiguring the entire set of memory cells to use one of the different read voltage thresholds in response to a read request for a sub-grouping associated with the one of the different read voltage thresholds.

18. The method of claim 14, further comprising sending the adjusted read voltage threshold to the non-volatile memory medium for each read operation for the set of storage cells.

19. The method of claim 14, wherein the one or more characteristics include one or more of a usage history for the set of memory cells, an error history for the set of memory cells, an age for the set of memory cells, a number of program and erase cycles for the set of memory cells, and an amount of wear for the set of memory cells.

20. The method of claim 14, further comprising detecting the shift in the read voltage level by detecting a data error for the set of memory cells.

21. The method of claim 14, further comprising detecting the shift in the read voltage level in response to a testing operation for the set of memory cells.