Nonvolatile memory device and method of programming the same

• US 8,854,887 B2
• Filed: 10/28/2011
• Issued: 10/07/2014
• Est. Priority Date: 07/10/2008
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Wang, Jong Hyun
• Primary Examiner(s): Nguyen, Tuan T
• Application Number:
  US13/283,760
• Publication Number:
  US 20120044761A1
• Time in Patent Office: 1,075 Days
• Field of Search: 365/185.18, 365/185.22, 365/185.03
• US Class Current: 365/185.18
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells

Abstract

A method of 4-bit MLC programming a nonvolatile memory device includes inputting an m^th program operation command and sequentially executing first to fourth logical page program operations according to first to fourth logical page program start voltages, each stored in first to fourth logical page program start voltage storage units, wherein a program voltage, which is applied at a time point at which a memory cell programmed higher than a lowest verify voltage while a program operation of each logical page is performed occurs for a first time, is updated to each logical page program start voltage.

Claims

1. A 4-bit MLC programming method of a nonvolatile memory device, the method comprising:

inputting an m^th program operation command; and

sequentially executing first to fourth logical page program operations according to first to fourth logical page program start voltages, each stored in first to fourth logical page program start voltage storage units,

wherein a program voltage, which is applied at a time point at which a memory cell programmed higher than a lowest verify voltage while a program operation of each logical page is performed occurs for a first time, is updated to each logical page program start voltage.

2. The 4-bit MLC programming method of claim 1, further comprising, when the (m+1)^th program operation command is executed, sequentially executing the first to fourth logical page program operations according to the updated first to fourth logical page program start voltages.

3. The 4-bit MLC programming method of claim 2, wherein the sequential execution of the respective logical page program operations includes repeatedly adding a step voltage to the program start voltage until target program cells are programmed higher than a verify voltage.

4. The 4-bit MLC programming method of claim 1, wherein the updating of the program voltage includes replacing a previously stored logical page program start voltage with a program voltage, which is applied at a time point at which a memory cell programmed higher than a verify voltage occurs for the first time.

5. The 4-bit MLC programming method of claim 1, wherein the first to fourth logical page program start voltage storage units comprise first to fourth page program start voltage storage units for storing different program start voltages on a page basis.

6. The 4-bit MLC programming method of claim 1, wherein the first to fourth logical page program start voltage storage units comprise first to n^th block program start voltage storage units for storing different program start voltages on a memory-cell-block basis.

7. The 4-bit MLC programming method of claim 1, wherein the first to fourth logical page program start voltage storage units comprise first to k^th chip program start voltage storage units for storing different program start voltages on a chip basis.

8. A nonvolatile memory device, comprising:

a plurality of a memory chips, each configured to include memory blocks including 4-bit or higher multi-level memory cells for storing data and peripheral circuits for programming the memory cells or reading data stored in the memory cells;

a program start voltage storage unit configured to store program start voltage information about each of the plurality of memory chips; and

a controller configured to repeat a program operation and a program verify operation for a page of the memory chip, selected in response to a program command, from among the pages, until a result of the program verify operation is a path, wherein, in the program operation, the controller supplies a program voltage raised by a step voltage from a program start voltage based on the program start voltage information, stored in the program start voltage storage unit and set based on the selected memory chip, to the selected page and controls the peripheral circuits and the program start voltage storage unit so that information based on a program voltage in a time point at which a memory cell for which the program operation is a pass is first generated, as a result of the program verify operation, is updated into the program start voltage information of the selected memory chip.

9. The nonvolatile memory device of claim 8, wherein, if the program start voltage storage unit stores program start voltage information about each of the memory blocks within each of the memory chips, the controller controls the peripheral circuits so that the program operation is performed by using the program start voltage information set according to a memory block including the selected page of the selected memory chip and updates the program start voltage information of the selected memory block within the selected memory chip.

10. The nonvolatile memory device of claim 8, wherein, if the program start voltage storage unit stores program start voltage information about each memory block within each of the memory chips and about each of pages within each memory block, the controller controls the peripheral circuits so that the program operation is performed by using the program start voltage information set according to a selected page of a selected memory block within the selected memory chip and updates the program start voltage information about the selected page of the selected memory block within the selected memory chip.

11. The nonvolatile memory device of claim 10, wherein the program start voltage storage unit stores program start voltage information about each memory block of each of the memory chips and about each logical page of each of the pages within each memory block.

12. A nonvolatile memory device, comprising:

a plurality of memory blocks each configured to include 4-bit or higher multi-level memory cells for storing data;

peripheral circuits configured to program the memory cells or read data stored in the memory cells;

a program start voltage storage unit configured to store program start voltage information about each of pages of each of the memory blocks; and

a controller configured to repeat a program operation and a program verify operation for a page selected in response to a program command, from among the pages, until a result of the program verify operation is a path, wherein, in the program operation, the controller supplies a program voltage, raised by a step voltage from a program start voltage based on the program start voltage information set based on the selected page, to the selected page and controls the peripheral circuits and the program start voltage storage unit so that information based on a program voltage in a time point at which a memory cell for which the program operation is a pass is first generated, as a result of the program verify operation, is updated into the program start voltage information of the selected memory chip.

13. The nonvolatile memory device of claim 12, wherein the program start voltage storage unit stores program start voltage information set for each logical pages of each of word lines of each memory block.

14. A method of programming a nonvolatile memory device, comprising:

receiving a program operation command to the nonvolatile memory device including 4-bit multi-level memory cells;

sequentially selecting first to fourth logical pages of a first word line, in response to a program operation command, and repeatedly performing a program operation and a program verify operation for the first word line until a result of the program verify operation is a path, wherein, in the program operation, a program voltage raised by a step voltage from a program start voltage based on program start voltage information set according to a selected logical page is supplied to the first word line and information about a program voltage supplied in a time point at which a memory cell for which the program operation is a path is first generated during the program verify operation is updated into the program start voltage information of the selected logical page.

15. The method of claim 14, further comprising sequentially selecting first to fourth logical pages of a second word line to be programmed after the first word line, in response to a program command for the second word line, and repeatedly performing a program operation and a program verify operation for the second word line until a result of the program verify operation is a path, wherein a program voltage for each logical page of the second word line is set in the program start voltage information of each of the first to fourth logical pages of the first word line which has been updated in the program operation.

16. The method of claim 14, further comprising:

erasing a memory block including the first word line, if the program start voltage set according to each of the first to fourth logical pages of the first word line is stored for every word line; and

performing the program operation for each of the first to fourth logical pages of the first word line based on the updated program start voltage information, when the program command for the first word line is received again.

17. The method of claim 14, wherein updating the information includes replacing previously stored program start voltage information with information about a program voltage which is supplied in a time point at which a memory cell programmed higher than a verify voltage is first generated.