Read self timing circuitry for self-timed memory
First Claim
1. A circuit, comprising:
- a memory cell array including;
a first section having a plurality of memory cells and a wordline for each row of memory cells in said first section; and
a second section having a plurality of read timer cells arranged in a column, each read timer cell including a reference wordline, a reference true bitline, an internal true node, an access transistor coupled between said internal true node and said reference true bitline and a pull-down transistor coupled between said internal true node and a reference supply node, wherein the reference true bitline is shared by the column of read timer cells;
a reference row decoder circuit coupled to the second section of the memory cell array, said reference row decoder circuit including a reference wordline driver circuit having an output coupled to drive the reference wordline; and
means for lowering a gate to source voltage of timer cell transistors by decreasing a higher voltage level corresponding to logic high that is applied on said reference wordline to actuate said at least one of said access transistor and pull-down transistor during a read operation of memory cells in the first section.
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Accused Products
Abstract
A self-timed memory includes a plurality of timer cells each including an access transistor coupled to a true node and having a gate coupled to a reference wordline actuated by a reference wordline driver. Self-timing is effectuated by detecting completion of reference true bitline discharge in the timer cells resulting in enabling a sense amplifier. To better align detected completion of the discharge by the timer cells to a read from actual memory cells at any voltage in the operating voltage range of the memory, the gate to source voltage of the timer cells'"'"' access transistors is lowered by decreasing the logic high voltage level applied by the reference wordline. The timer cells may also, or alternatively, have pulldown transistors coupled to the internal true node, wherein a gate terminal of the pulldown is coupled to the reference wordline node and activated with the lowered gate to source voltage.
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Citations
25 Claims
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1. A circuit, comprising:
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a memory cell array including; a first section having a plurality of memory cells and a wordline for each row of memory cells in said first section; and a second section having a plurality of read timer cells arranged in a column, each read timer cell including a reference wordline, a reference true bitline, an internal true node, an access transistor coupled between said internal true node and said reference true bitline and a pull-down transistor coupled between said internal true node and a reference supply node, wherein the reference true bitline is shared by the column of read timer cells; a reference row decoder circuit coupled to the second section of the memory cell array, said reference row decoder circuit including a reference wordline driver circuit having an output coupled to drive the reference wordline; and means for lowering a gate to source voltage of timer cell transistors by decreasing a higher voltage level corresponding to logic high that is applied on said reference wordline to actuate said at least one of said access transistor and pull-down transistor during a read operation of memory cells in the first section. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. Self-timing circuitry for use in a memory, said memory including a plurality of memory cells, comprising:
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a plurality of timer cells arranged in a column; a reference true bitline coupled to the column of write timer cells; a reference wordline for each timer cell in the column; wherein each timer cell includes an internal true node, an access transistor coupled between said internal true node and said reference true bitline and a pull-down transistor coupled between said internal true node and a reference supply node; a reference wordline driver circuit having an output coupled to said reference wordline; a detection circuit coupled to said reference true bitline and having an output whose logic state changes in response to completion of discharge of the reference true bitline during a read operation; and a circuit configured to lower a gate to source voltage of timer cell transistors by decreasing a higher voltage level corresponding to logic high, the decreased voltage for application on said reference wordline to actuate at least one of said access transistor and pull-down transistor during a read operation of memory cells in the memory. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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18. A method, comprising:
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reading a logic value from a true side of a timer cell of a self-timed memory, said timer cell including an access transistor coupled between an internal true node and a reference true bitline and a pull-down transistor coupled between said internal true node and a reference supply node; detecting a completion of a discharge of the reference true bitline by the read timer cell of the self-timed memory; signaling an enabling of a sense amplifier operation of the self-timed memory in response to detected discharge completion; and lowering a gate to source voltage of a read timer cell transistor by decreasing a higher voltage level corresponding to logic high, the decreased voltage for application on said reference wordline to actuate at least one of said access transistor and pull-down transistor during said logic value read. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25)
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Specification