Write self timing circuitry for self-timed memory

• US 8,854,902 B2
• Filed: 05/18/2012
• Issued: 10/07/2014
• Est. Priority Date: 05/18/2012
• Status: Active Grant

• Current Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Original Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Inventors: Kohli, Nishu
• Primary Examiner(s): Luu, Pho M
• Application Number:
  US13/474,825
• Publication Number:
  US 20130308399A1
• Time in Patent Office: 872 Days
• Field of Search: 365/189.16, 365/189.11, 365/241, 365/210.1, 365/210.14
• US Class Current: 365/189.16
• CPC Class Codes: G11C 11/413 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/0475 comprising two or more independent storage sites which store independent data
• CPC Class Codes: G11C 7/227 Timing of memory operations based on dummy memory elements or replica circuits

Abstract

A self-timed memory includes a plurality of write timer cells. A reference write driver circuit writes a logic low value to a true side of the write timer cells. Each write timer cell includes a pullup transistor whose gate is coupled to an internal true node. Self-timing is effectuated by detecting a completion of the logic value write at a complement side of the write timer cells and signaling a reset of the self-timer memory in response to detected completion. To better align detected completion of the write in write timer cells to actual completion of a write in the memory, a gate to source voltage of the write timer cell pullup transistor is lowered by increasing a lower logic level voltage at the internal true node in connection with driver circuit operation to write a low logic state into the true side of the write timer cell.

Claims

1. A circuit, comprising:

a memory cell array including;

a first section having a plurality of memory cells and at least one data bit line for each column of memory cells in said first section; and

a second section having a plurality of write timer cells arranged in a column, each write timer cell including an internal true node, an internal complement node and a pullup transistor having a gate terminal coupled to said internal true node, said second section including at least one reference bit line coupled to the column of write timer cells and having a true reference internal line coupled to the internal true nodes of the column of write timer cells;

column circuitry coupled to the first and second sections of the memory cell array, said column circuitry including a reference write driver circuit having an output coupled to drive said at least one reference bit line; and

means for lowering a gate to source voltage of the write timer cell pullup transistor by raising a lower voltage level to which said internal true node is pulled down during a write operation to a voltage level above logic low level.

2. The circuit of claim 1, wherein a raised lower voltage level applied to said internal true node is equal to a ground reference voltage plus a delta voltage value.

3. The circuit of claim 2, wherein the delta voltage value is equal to an estimated shift in threshold voltage of a pullup transistor in a memory cell with a statistically worst write time among the plurality of memory cells in the first section of the memory cell array.

4. The circuit of claim 1, wherein raising the lower voltage level of said internal true node occurs in connection with reference write driver operation to write a low logic state to the internal true node of the write timer cell.

5. The circuit of claim 1, wherein the means for lowering comprises a voltage raising circuit coupled between a ground supply node and a lower supply node of said reference write driver circuit, said voltage raising circuit operable to apply a lower supply voltage to said lower supply node which is equal to a ground reference voltage plus a delta voltage value.

6. The circuit of claim 5, wherein the delta voltage value is equal to an estimated shift in threshold voltage of a pullup transistor in a memory cell with a statistically worst write time among the plurality of memory cells in the first section of the memory cell array.

7. The circuit of claim 1, wherein the means for lowering comprises a pullup circuit coupled to the at least one reference bit line and configured to limit a lower logic voltage applied by the write driver circuit to said at least one reference bit line to a value which is equal to a ground reference voltage plus a delta voltage value.

8. The circuit of claim 7, wherein the delta voltage value is equal to an estimated shift in threshold voltage of a pullup transistor in a memory cell with a statistically worst write time among the plurality of memory cells in the first section of the memory cell array.

9. The circuit of claim 7, wherein the pullup circuit comprises a pullup resistance coupled between the at least one reference bit line and a high supply voltage.

10. The circuit of claim 1, wherein the means for lowering comprises a pullup circuit coupled to the true reference internal line and configured to limit a lower logic voltage at said internal true node to a value which is equal to a ground reference voltage plus a delta voltage value.

11. The circuit of claim 10, wherein the delta voltage value is equal to an estimated shift in threshold voltage of a pullup transistor in a memory cell with a statistically worst write time among the plurality of memory cells in the first section of the memory cell array.

12. The circuit of claim 10, wherein the pullup circuit comprises a pullup resistance coupled between the true reference internal line and a high supply voltage.

13. The circuit of claim 1, further including a complement reference internal line coupled to the internal complement nodes of the column of write timer cells.

14. The circuit of claim 13, wherein the column circuitry further comprises a detecting circuit coupled to said complement reference internal line and having an output whose logic state changes in response to said write timer cells indicating completion of a write operation.

15. Self-timing circuitry for use in a memory, said memory including a plurality of memory cells, comprising:

a plurality of write timer cells arranged in a column, each write timer cell including a reference word line shared in common with said write timer cells, an internal true node, an internal complement node and a pullup transistor having a gate terminal coupled to said internal true node;

a reference bit line coupled to the column of write timer cells;

a complement reference internal line coupled to the internal complement nodes of the column of write timer cells;

a reference write driver circuit having an output coupled to said reference bit line and configured to initiate a write operation in said write timer cells;

a detecting circuit coupled to said complement reference internal line and having an output whose logic state changes in response to completion of said write operation in said write timer cells; and

a circuit configured to lower a gate to source voltage of the write timer cell pullup transistors by raising a lower logic level voltage to which said internal true nodes are pulled down during a write operation to a voltage level above logic low level.

16. The circuit of claim 15, wherein a raised lower logic level voltage for said internal true nodes is equal to a ground reference voltage plus a delta voltage.

17. The circuit of claim 16, wherein the delta voltage value is equal to an estimated shift in threshold voltage of a pullup transistor in a memory cell of the plurality of memory cells with a statistically worst write time.

18. The circuit of claim 16, wherein said circuit comprises a voltage raising circuit coupled between a ground reference and a lower supply node of said reference write driver circuit, said voltage raising circuit operable to apply a lower supply voltage to said lower supply node which is equal to the ground reference voltage plus the delta voltage.

19. The circuit of claim 16, wherein said circuit comprises a pullup circuit coupled between a high supply reference and the reference bit line, said pullup circuit configured to limit a lower voltage applied on said reference bit line to the ground reference voltage plus the delta voltage.

20. The circuit of claim 19, wherein the pullup circuit comprises a pullup resistance coupled between the high supply reference and the reference bit line.

21. The circuit of claim 16, further comprising a true reference internal line coupled to the internal true nodes of the column of write timer cells;

and

wherein said circuit comprises a pullup circuit coupled between a high supply reference and the true reference internal line, said pullup circuit configured to limit a lower voltage applied to said internal true nodes to the ground reference voltage plus the delta voltage.

22. The circuit of claim 21, wherein the pullup circuit comprises a pullup resistance coupled between the high supply reference and the true reference internal line.

23. The circuit of claim 15, wherein the raising of the lower logic level voltage for said internal true nodes occurs in connection with reference write driver operation to write a low logic state to the internal true nodes of the write timer cells.

24. A method, comprising:

writing a first logic value to a true side of a write timer cell of a self-timed memory, said write timer cell including a pullup transistor having a gate terminal coupled to an internal true node;

detecting a completion of a second logic value write at a complement side of the write timer cell of the self-timed memory;

signaling a write reset of the self-timer memory in response to detected completion; and

lowering a gate to source voltage of the write timer cell pullup transistor by raising a lower logic level voltage to which said internal true node is pulled down during a write operation to a voltage level above logic low level.

25. The method of claim 24, wherein lowering adjusts a timing of completion of the writing to the write timer cell to better match a timing for completion of writing to a memory cell within the self-timed memory with a statistically worst write time.

26. The method of claim 24, wherein a raised lower logic level voltage for said internal true node is equal to a ground reference voltage plus a delta voltage.

27. The method of claim 26, wherein the delta voltage value is equal to an estimated shift in threshold voltage of a pullup transistor in a memory cell within said self-timed memory with a statistically worst write time.

28. The method of claim 24, wherein raising comprises raising a lower supply voltage for a reference write driver circuit that is operable to perform the step of writing the first logic value.

29. The method of claim 24, wherein raising comprises pulling up a lower voltage on a reference bit line to a value above ground in connection with writing a low logic state into the true side of the write timer cell.

30. The method of claim 24, wherein raising comprises pulling up a lower voltage on said internal true node to a value above ground in connection with writing a low logic state into the true side of the write timer cell.