Reconfigurable and customizable general-purpose circuits for neural networks
First Claim
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1. A reconfigurable neural network circuit, comprising:
- an electronic synapse array comprising multiple digital synapses interconnecting a plurality of digital electronic neurons, wherein each neuron comprises an integrator that integrates input spikes and generates a spike signal when the integrated input spikes exceed a threshold;
a first learning module and a second learning module for reconfiguring a pre-synaptic neuron and a post-synaptic neuron, respectively, in the synapse array, wherein each learning module is independently reconfigurable; and
a control module for reconfiguring the synapse array, the control module comprising a global finite state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons among said neurons, to sequentially access the synapse array.
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Abstract
A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.
43 Citations
27 Claims
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1. A reconfigurable neural network circuit, comprising:
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an electronic synapse array comprising multiple digital synapses interconnecting a plurality of digital electronic neurons, wherein each neuron comprises an integrator that integrates input spikes and generates a spike signal when the integrated input spikes exceed a threshold; a first learning module and a second learning module for reconfiguring a pre-synaptic neuron and a post-synaptic neuron, respectively, in the synapse array, wherein each learning module is independently reconfigurable; and a control module for reconfiguring the synapse array, the control module comprising a global finite state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons among said neurons, to sequentially access the synapse array. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A reconfigurable neural network circuit, comprising:
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an electronic synapse array comprising multiple digital synapses interconnecting a plurality of digital electronic neurons, wherein each neuron comprises an integrator that integrates input spikes and generates a spike signal when the integrated input spikes exceed a threshold; and a control module for reconfiguring the synapse array, the control module comprising a global finite state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons among said neurons, to sequentially access the synapse array; wherein each synapse comprises a multi-bit synapse including multiple transposable 1-bit static random access memory cells. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27)
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Specification