Mixed-mode multiplier using hard and soft logic circuitry

• US 8,856,201 B1
• Filed: 04/16/2012
• Issued: 10/07/2014
• Est. Priority Date: 11/10/2004
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Langhammer, Martin, Lee, Kwan Yee Martin, Burney, Ali H.
• Primary Examiner(s): Malzahn, David H
• Application Number:
  US13/447,687
• Time in Patent Office: 904 Days
• Field of Search: None
• US Class Current: 708/620
• CPC Class Codes: G06F 7/5318 with column wise addition of partial products, e.g. using Wallace tree, Dadda counters G06F7/5324 takes precedence
• CPC Class Codes: H03K 19/17732 Macroblocks
• CPC Class Codes: H03K 19/17736 Structural details of routing resources

Abstract

Multiplier circuitry that efficiently utilizes the hard and soft logic regions of a programmable logic device (PLD) is provided. The multiplier circuitry includes a partial product generation block, a compression block (e.g., a carry-save adder), and an carry-propagate adder stage. The partial product generation and compression block are implemented in hard logic while the carry-propagate adder is implemented in soft logic. Local or global routing may be used to connect the hard and soft multiplier components. The multiplier may further include a selectable input register in hard logic and/or a selectable output register in soft logic. This mixed-mode design allows for a substantial savings in the amount of hard logic required to implement the multiplier without a significant decrease in multiplier performance.

Claims

1. A programmable device comprising:

an array of user-configurable logic regions arranged in rows and columns, each of said user-configurable logic regions having a first height dimension;

at least one non-configurable logic region located within said array and being preconfigured to perform at least one, and fewer than all, functions needed to perform a multiplication operation, each said at least one non-configurable logic region having a second height dimension equal to an integral number of said first height dimension; and

a network of user-configurable interconnection conductors for conveying signals to, from and among said logic regions;

wherein;

additional functions needed, with said functions performed by said non-configurable logic region, to perform a multiplication operation, are configurable using a particular number of said user-configurable logic regions; and

said second height dimension is designed so that said integral number is equal to said particular number;

whereby;

one of said at least one non-configurable logic region, together with a group of said user-configurable logic regions adjacent to said one of said at least one non-configurable logic region, said group being of said particular number, are configurable, using said network of interconnection conductors, to perform a multiplication operation in a substantially rectangular portion of said programmable device.

2. The programmable device of claim 1 wherein said at least one non-configurable logic region is coupled to said particular number of said user-configurable logic regions by global routing.

3. The programmable device of claim 1 wherein said at least one non-configurable logic region is coupled to said particular number of said user-configurable logic regions by local routing.

4. The programmable device of claim 1 wherein:

said substantially rectangular portion has a height dimension; and

said height dimension is determined by a number of user-configurable logic regions that are required to generate inputs to said multiplication operation.

5. The programmable device of claim 1 wherein:

said at least one non-configurable logic region comprises circuitry that is operative to generate partial product terms, the sum of which is the product of the multiplication operation component.

6. The programmable device of claim 5 wherein said at least one non-configurable logic region further comprises circuitry that is operative to compress the partial product terms to generate at least two compressed vectors.

7. The programmable device of claim 6 wherein the circuitry that is operative to compress the partial product terms to generate at least two compressed vectors comprises a carry-save adder.

8. The programmable device of claim 7 wherein the carry-save adder is arranged in a Wallace tree configuration.

9. The programmable device of claim 6 wherein a group of at least one of said user-configurable logic regions is configured as circuitry operative to generate an output product term based on the at least two compressed vectors.

10. The programmable device of claim 9 wherein the circuitry that is operative to generate the output product term based on the at least two compressed vectors comprises a carry-propagate adder.

11. A method of configuring a multiplication operation in a programmable device, said programmable device having an array of user-configurable logic regions arranged in rows and columns, each of said user-configurable logic regions having a first height dimension;

at least one non-configurable logic region located within said array and being preconfigured to perform at least one, and fewer than all, functions needed to perform a multiplication operation, each said at least one non-configurable logic region having a second height dimension equal to an integral multiple of said first height dimension; and

a network of user-configurable interconnection conductors for conveying signals to, from and among said logic regions;

said method comprising;

selecting a group of said user-configurable logic regions adjacent to one of said at least one non-configurable logic region, said group being of a number corresponding to said integral multiple;

configuring said group of user-configurable logic regions to perform additional functions needed, in addition to said functions performed by said non-configurable logic region, to perform a multiplication operation; and

configuring said network of interconnection conductors to interconnect said group of user-configurable logic regions and said one of said at least one non-configurable logic region to perform a multiplication operation in a substantially rectangular portion of said programmable device.

12. The method of claim 11 wherein said configuring said network of interconnection conductors comprises coupling said at least one non-configurable logic region to said group of said user-configurable logic regions by global routing.

13. The method of claim 11 wherein said configuring said network of interconnection conductors comprises coupling said at least one non-configurable logic region to said group of said user-configurable logic regions by local routing.

14. The method of claim 11 wherein:

said substantially rectangular portion has a height dimension; and

said height dimension is determined by a number of user-configurable logic regions that are required to generate inputs to said multiplication operation.

15. The method of claim 11 wherein:

said at least one non-configurable logic region comprises circuitry that is operative to generate partial product terms, the sum of which is the product of the multiplication operation component, and circuitry that is operative to compress the partial product terms to generate at least two compressed vectors; and

said configuring said group of user-configurable logic regions to perform additional functions needed comprises configuring circuitry that is operative to generate an output product term based on the at least two compressed vectors.

16. The method of claim 15 wherein configuring circuitry that is operative to generate an output product term based on the at least two compressed vectors comprises configuring at least a portion of said group of user-configurable logic regions as a carry-propagate adder.