Universal controller for peripheral devices in a computing system

• US 8,856,401 B2
• Filed: 06/29/2004
• Issued: 10/07/2014
• Est. Priority Date: 11/25/2003
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Azadet, Kameran, Truman, Thomas
• Primary Examiner(s): Unelus, Ernest
• Application Number:
  US10/880,331
• Publication Number:
  US 20050114581A1
• Time in Patent Office: 3,752 Days
• Field of Search: 710/8, 710/305, 710/11, 710/63, 710/315, 370/463, 370/469, 370/465, 709/250, 709/230
• US Class Current: 710/36
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: H04L 69/14 Multichannel or multilink protocols

Abstract

An integrated controller is provided for controlling communications with a plurality of peripheral devices. The integrated controller includes a bus interface for processing communications with a processor; a switch for routing communications between the processor and one or more of the peripheral devices; and a plurality of controllers, where each of the controllers provide an interface to at least one peripheral device. The controllers include at least one PHY controller for a corresponding peripheral device that provides an electrical interface to a connection, such as a network connection. The controllers also include at least one MAC controller that stores and forwards packets to and from a network connection.

Claims

1. An integrated controller for communicating with a plurality of physical (PHY) layer peripheral devices, comprising:

a bus interface for processing communications with a central processing unit, wherein said central processing unit is external to said integrated controller;

a switch for routing communications between said central processing unit and one or more of said plurality of peripheral devices; and

a plurality of Media Access Controller (MAC)/PHY controllers, each of said MAC/PHY controllers providing both MAC and PHY functions and an interface to at least one peripheral device and translating said communications into a format suitable for said at least one peripheral device such that said integrated controller supports a plurality of standards in a physical (PHY) layer, wherein said plurality of MAC/PHY controllers comprise a plurality of MAC controllers configured to support different standards simultaneously via a demultiplexer.

2. The integrated controller of claim 1, wherein at least one of said plurality of MAC/PHY controllers includes a PHY controller for a corresponding peripheral device.

3. The integrated controller of claim 2, wherein said PHY controller provides an electrical interface to a connection.

4. The integrated controller of claim 1, wherein at least one of said plurality of MAC/PHY controllers includes a MAC controller for a corresponding peripheral device.

5. The integrated controller of claim 4, wherein said MAC controller stores and forwards packets to and from a network.

6. The integrated controller of claim 1, wherein said plurality of MAC/PHY controllers translate said communications into a format suitable for said corresponding peripheral devices.

7. The integrated controller of claim 1, wherein said communications are in accordance with a PCI-Express standard.

8. The integrated controller of claim 1, wherein said bus interface provides said communications to said central processing unit via a North bridge.

9. The integrated controller of claim 1, wherein said bus interface provides said communications to said central processing unit via a South bridge.

10. The integrated controller of claim 1, wherein said integrated controller is embodied on an integrated circuit.

11. The integrated controller of claim 1, wherein said integrated controller is a System on a Chip.

12. The integrated controller of claim 1, wherein said plurality of physical (PHY) layer standards comprise one or more of Ethernet, Wireless Fidelity (WiFi), Universal Serial Bus (USB) and Firewire technologies.

13. An integrated circuit, comprising:

a bus interface for processing communications with a central processing unit, wherein said central processing unit is external to said integrated circuit;

a switch for routing communications between said central processing unit and one or more of said plurality of physical (PHY) layer peripheral devices;

a plurality of Media Access Controller (MAC)/PHY controllers, each of said MAC/PHY controllers providing both MAC and PHY functions and an interface to at least one peripheral device and translating said communications into a format suitable for said at least one peripheral device such that said integrated controller supports a plurality of physical (PHY) layer standards, wherein said plurality of MAC/PHY controllers comprise a plurality of MAC controllers configured to support different standards simultaneously via a demultiplexer.

14. The integrated circuit of claim 13, wherein at least one of said plurality of MAC/PHY controllers includes a PHY controller for a corresponding peripheral device.

15. The integrated circuit of claim 14, wherein said PHY controller provides an electrical interface to a connection.

16. The integrated circuit of claim 13, wherein at least one of said plurality of MAC/PHY controllers includes a MAC controller for a corresponding peripheral device.

17. The integrated circuit of claim 16, wherein said MAC controller stores and forwards packets to and from a network.

18. The integrated circuit of claim 13, wherein said plurality of MAC/PHY controllers translate said communications into a format suitable for said corresponding peripheral devices.

19. The integrated circuit of claim 13, wherein said communications are in accordance with a PCI-Express standard.

20. The integrated circuit of claim 13, wherein said bus interface provides said communications to said central processing unit via a North bridge.

21. The integrated circuit of claim 13, wherein said bus interface provides said communications to said central processing unit via a South bridge.

22. A method performed by an integrated device for communicating with a plurality of peripheral devices, comprising:

processing communications with a central processing unit that is external to said integrated device;

routing communications between said central processing unit and one or more of said plurality of physical (PHY) layer peripheral devices; and

providing an interface to said plurality of peripheral devices using a plurality of Media Access Controller (MAC)/PHY controllers, wherein said plurality of MAC/PHY controllers provide both MAC and PHY functions and translate said communications into a format suitable for said at least one peripheral device such that said integrated device supports a plurality of physical (PHY) layer standards, wherein said plurality of MAC/PHY controllers comprise a plurality of MAC controllers configured to support different standards simultaneously via a demultiplexer.

23. The method of claim 22, wherein said providing step is performed by a PHY controller associated with a corresponding peripheral device.

24. The method of claim 22, further comprising the step of storing and forwarding packets to and from a network.

25. The method of claim 22, wherein said providing step further comprises the step of translating said communications into a format suitable for given peripheral device.

26. The method of claim 22, wherein said communications are in accordance with a PCI-Express standard.